Blind Via Interposer Grounding With Composite Resistivity Structure
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing interposer designs face issues with high insertion loss and ground uniformity at high frequencies due to non-negligible impedance and cross-talk from wire bonds, and the use of through-silicon vias (TSVs) is limited by manufacturing complexity and thermal stress, while metallizing sides of the interposer requires additional steps and increased cost.
Innovation Solution
An interposer with a composite substrate featuring high-resistivity and low-resistivity portions, utilizing blind via-holes for direct conductive paths between grounding patterns, reducing the length of electrical connections and eliminating the need for bonding wires or TSVs, with a conductive layer on the via-hole sidewalls and optional filling to prevent impurities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonds are used to connect grounding pattern on interposer to ground on mounting substrate, then grounding is achieved, but cross-talk is generated between bonding wires and impedance is non-negligible
Solution Approach 1:
The patent extracts the harmful wire bond connections from the grounding system and replaces them with direct substrate-based grounding paths. The wire bonds are completely removed and replaced by conductive patterns on the substrate surface and through-silicon vias, eliminating the source of cross-talk while maintaining grounding functionality.
Solution Approach 2:
The patent introduces an intermediary grounding structure consisting of conductive patterns on the substrate surface and through-silicon vias filled with conductive material. This intermediary structure serves as a mediator between the grounding pattern on the interposer and the ground on the mounting substrate, providing a lower-impedance path without the cross-talk issues of wire bonds.
2Reliability
If wire bonds are used for grounding, then grounding connection is established, but length of wire bonds increases inductive behaviour and footprint is increased
Solution Approach 1:
The patent removes the lengthy wire bond connections and replaces them with compact grounding paths embedded within the substrate. The grounding connection is achieved through conductive patterns on the substrate surface and short through-silicon vias, dramatically reducing the length of the grounding path and eliminating the inductive behavior associated with long wire bonds.
Solution Approach 2:
The patent transitions from three-dimensional wire bond connections to two-dimensional conductive patterns on the substrate surface combined with vertical through-silicon vias. This dimensional change allows the grounding path to be embedded within the substrate volume, reducing the overall length and inductance while maintaining effective grounding connection.
3Reliability
If through-silicon vias are used to achieve grounding, then direct connection is obtained, but additional manufacturing steps are required and complexity increases
Solution Approach 1:
The patent merges the formation of through-silicon vias with the existing substrate processing steps. The vias are created during the same manufacturing sequence as other substrate modifications, and the conductive filling is integrated with the existing conductive pattern deposition processes, thereby reducing additional manufacturing complexity while achieving direct grounding connections.
Solution Approach 2:
The patent designs the through-silicon via structure to serve multiple functions: providing direct grounding connection, serving as a via for subsequent electrical connections, and acting as a stress relief feature. This multi-functionality reduces the need for separate manufacturing steps and structures, thereby reducing overall manufacturing complexity.
4Reliability
If through-silicon vias are used for grounding, then grounding path is established, but footprint occupied and manufacturing aspect ratio limitations are encountered
Solution Approach 1:
The patent applies local quality by creating through-silicon vias only at specific locations where grounding connections are needed, rather than using large-area wire bonds. The vias are concentrated in small footprint regions, providing effective grounding paths while occupying minimal area on the circuit board, thus resolving the contradiction between reliable grounding and small footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This structure achieves reduced impedance and improved ground uniformity, minimizing electrical losses and manufacturing complexity, while maintaining a compact footprint and integrating seamlessly with existing processes.
Implementation Method 1
a high-resistivity portion extending from said first surface into the bulk of the substrate, and a low-resistivity portion extending from the high-resistivity portion to a second surface of the substrate
Implementation Method 2
electrically-conductive structure is provided in the blind via-hole(s) and interconnects the conductive pattern on the first surface of the substrate with the low resistivity portion of the substrate
Data Source
Figure 1~2
Figure 3~4
Figure 5~6
AI summary
A current path is provided through an interposer (1) by exploiting an interposer substrate that has a high-resistivity portion (10a) at a first surface (10c) of the interposer and a low-resistivity portion (10b) extending from the high-resistivity portion to a second surface (10d) of the interposer. A set of blind via-holes (15) comprising electrically-conductive material (e.g. doped sidewalls) extend from the first surface (10c) of the interposer substrate through the high-resistivity portion (10a) thereof and into the low-resistivity portion (10b). Top-to-bottom connection can be made using the conductive material in the blind vias (15) and using the low-resistivity portion (10b) of the interposer substrate, while the high-resistivity portion (10a) of the interposer substrate impedes current leakage from the first surface (10c) of the substrate to the second surface (10d) of the substrate.