Block Decoder Prevents Leakage Current in Semiconductor Memory
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Solution Overview
Problem
Semiconductor memory devices face malfunction due to leakage currents, which discharge precharged bit lines through unselected memory cell blocks, leading to errors during sensing operations.
Innovation Solution
A semiconductor memory device design that includes a block decoder and block switch, which controls the drain select transistor, source select transistor, and side word line transistors to prevent leakage currents by generating and applying appropriate control signals to select and disconnect memory cell blocks from global word lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If unselected memory cell blocks are disconnected from global word lines, then device complexity is reduced, but leakage currents still flow through memory cells causing sensing errors
Solution Approach 1:
The patent segments the word line selection control into two levels: block-level selection through block decoders and cell-level selection through row decoders. This segmentation allows unselected blocks to be disconnected at the block level while maintaining the ability to selectively activate specific cells within selected blocks, preventing leakage currents without compromising sensing accuracy.
Solution Approach 2:
The patent introduces row decoders as intermediary components between block decoders and memory cells. These row decoders receive block select signals and generate row select signals that control individual cell access. This intermediary layer ensures that only cells in selected blocks are active, preventing leakage currents from unselected blocks while maintaining proper cell selection functionality.
2Reliability
If block decoder outputs block select signals to control transistors, then leakage currents are prevented, but device complexity increases due to additional control signals
Solution Approach 1:
The patent merges the block selection function with the transistor control function by directly outputting block select signals from the block decoder to control the drain select, source select, and side word line transistors. This integration eliminates the need for separate control signal paths, reducing overall device complexity while effectively preventing leakage currents through unselected blocks.
Solution Approach 2:
The block select signals serve multiple functions: they control the block switch to connect/disconnect global word lines, activate row decoders for cell selection, and control select transistors to prevent leakage. This multi-functionality reduces the number of separate control mechanisms needed, balancing reliability improvements with complexity management.
3Reliability
If all transistors in unselected blocks are turned off, then leakage currents are eliminated, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies local quality control by turning off transistors selectively based on block selection status. Row decoders generate row select signals that locally control transistors within selected blocks while leaving transistors in unselected blocks turned off. This localized control approach eliminates leakage currents without requiring uniform precision across all transistors, as only transistors in active blocks need precise control during operation.
Data Source
AI summary
A semiconductor memory device can improve electrical properties by prohibiting a leakage current, which flows through a memory cell, in such a way as to turn off a drain select transistor, a source select transistor and a side transistor of an unselected memory cell block when the semiconductor memory device operates. The semiconductor memory device includes a memory cell block in which a plurality of memory cells, drain and source select transistors, and side word line transistors are connected in a string structure, a block decoder for outputting a block select signal in response to predecoded address signals and controlling the drain and source select transistors and the side word line transistors, and a block switch for connecting a global word line to word lines of the memory cell block in response to the block select signal.