Read-Only Memories TRIZ Cases

Dummy word lines buffer ground select lines from memory strings, reducing leakage currents and erase disturbances while maintaining high integration density.

Dynamically adjusting target erase levels prevents over-erase damage and reduces operation time for degraded memory cells.

A fuse circuit uses a variable resistor sensing unit to detect programmed states and identify defective fuses for replacement.

Ready busy signal generator switches between internal and external signals to resolve controller miscommunication from status ambiguity.

Shared gate structures and active regions for ground transistors compress peripheral circuit area while maintaining independent control capability.

Storing initial latch data in nonvolatile memory configures storage device latches, reducing standby leakage currents during reduced power modes.

Two-phase programming splits cell levels to store non-integer bits, improving storage density while maintaining integer-based decoding simplicity.

A one-time programmable fuse cell uses a select transistor and programming transistor to break down the fuse and sense current directly.

Merging register functions via time-division multiplexing reduces memory chip area while supporting increased setting-change allowable states.

Segmenting the synapse into a memristive storage device and an optical modulator reduces manufacturing complexity compared to direct optical weight integration.

Segmented row latches count stress events to generate specific addresses, resolving row hammer induced bit flips without lowering refresh throughput.

Skipping upper page writes prevents simultaneous destruction of lower page data, resolving reliability degradation caused by unexpected power interruptions.

Current sensing replaces voltage detection to eliminate bit line precharging, reducing read cycle time and power consumption while improving noise immunity.

An intermediate SRCGND voltage stabilizes the bit line to reduce current consumption while maintaining fast read operation speed.

A single magnetic tunnel junction stack serves dual memory functions through a gating transistor, minimizing integration complexity.

A non-volatile memory device uses a crossbar and dynamic page buffers to route data for concurrent read and write operations.

A semiconductor memory apparatus monitors MOS transistor characteristics to regulate internal bias voltage.

A memory controller uses a shift table to adjust read voltages for non-volatile memory access.

Opposite polarity stabilization voltage accelerates charge distribution, reducing threshold voltage settling time and improving programming accuracy.

An ECG extension cable uses a switching element to redirect the ground path along a bypass path, enabling uninterrupted data transmission.

A non-volatile semiconductor storage device uses segmented write modes to charge bit lines without applying program pulses.

Segmenting the memory array and placing transfer circuits between sections reduces global line area and power consumption while maintaining bandwidth.

Block decoder turns off drain and source select transistors to stop leakage currents that discharge precharged bit lines during sensing operations.

Ramping the pass voltage on unselected word lines maintains channel boosting levels, reducing program disturb caused by leakage and temperature variations.

Adding capacitance to bit lines suppresses coupling noise and prevents unintended activation during low voltage operations.

Dynamic plate line potential control via oxide semiconductor transistors suppresses leak currents that degrade data retention in silicon-based memory devices.

Peripheral circuit executes dummy operations on unselected planes, maintaining uniform operating voltage characteristics during single plane memory access.

Applying a positive boost voltage to the data line enables sensing of negative threshold cells without complex negative voltage generation circuitry.

Tracked elapsed time via trits selects demarcation voltages, managing threshold voltage drift while reducing storage overhead.

Shared row decoders couple multiple memory cell arrays to common conductive lines, suppressing chip area expansion while maintaining independent array access.

Unipolar ReRAM programming uses a transistor to limit current, eliminating leakage and material stress from reverse biasing.

A memory controller identifies malfunction states from threshold voltage distributions to set optimal read voltages.

A data transfer throttling arrangement shapes power usage by measuring bandwidth thresholds and delaying write activities during peak periods.

Segmented page buffers reduce power consumption by enabling only necessary groups, optimizing access time for data smaller than a full page.

Controller allocates buffer memory storage space after read operation completion, eliminating latency and improving utilization efficiency.

Pre-charges bit lines with bias voltage close to ideal levels, reducing sensing delay and power consumption while maintaining performance.

Segmenting the write operation into initial and final threshold distribution stages reduces data transfer time while maintaining storage capacity.

Offsetting the ferromagnetic layer center of gravity and adding silicon nitride insulation reduces temperature rise, preventing write errors.

A radiation-hardened e-fuse macro uses self-timed control circuitry to enable asynchronous operation without external clock signals.

Control logic selectively applies erase voltage to bit lines to decrease threshold voltages of affected memory cells, resolving program disturb issues.

Delaying selected wordline activation settles unselected lines, reducing resistive-capacitive coupling and improving read threshold voltage margins.

Assist circuit trimming selectively activates support circuits based on bit functionality to reduce active power consumption in memory arrays.

Premature data loading enables flip-bit detection for optimized read voltage adjustments, correcting erroneous voltages to improve data accuracy.

A resistive sense memory structure uses shared bit lines and source lines to reduce line resistivity.

A non-volatile memory programming method uses verification pulses to check cell states and terminates the process when unverified cells fall below an error correction threshold.

Hierarchical address segmentation reduces decoding circuit area and word line selection delay time in semiconductor memory devices.

Bistable circuits hold memory cell copies for testing, eliminating dedicated input-output circuits and reducing device complexity.