Single MTJ Stack Design for MRAM and OTP Memory Integration
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Solution Overview
Problem
Designing an MTJ stack that excels in all performance requirements for MRAM cells is challenging, as different stacks are needed for various applications, leading to increased integration costs.
Innovation Solution
A single MTJ stack and a gating MOS transistor are used to create both MRAM and one-time-programmable (OTP) memory cells, with the MTJ stack optimized for specific applications and the MOS transistor being identical, allowing for distinct memory types in a single integrated circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If different MTJ stacks are used for different applications (MRAM and OTP memory), then each memory type can be optimized for its specific performance requirements, but the integration costs and device complexity increase
Solution Approach 1:
The patent applies universality by designing a single MTJ stack structure that can serve dual purposes: functioning as both MRAM cells (with reversible magnetization) and OTP memory cells (with irreversible magnetization). The same basic stack components (reference layer, tunnel barrier, free layer, capping layer) are used for both memory types, allowing one structure to perform multiple functions. This reduces integration complexity while maintaining optimized performance for both application types through software-controlled programming modes.
2Ease of manufacture
If a single MTJ stack is used for both MRAM and OTP memory, then integration costs are minimized, but the ability to optimize each memory type for its specific application is reduced
Solution Approach 1:
The patent applies local quality by introducing a controllable magnetic field gradient or current-induced field at specific locations within the MTJ stack during programming operations. This allows the same physical stack to exhibit different magnetic properties locally: in MRAM mode, the field enables reversible magnetization switching for writable memory; in OTP mode, the field creates irreversible magnetization states for one-time programming. The local field modification is achieved through selective application of programming currents or external magnetic fields during fabrication or operation, enabling both memory types to function optimally from a single stack structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of integrated circuits with both MRAM and OTP memory arrays, achieving fast read/write speeds, low power consumption, non-volatility, and high endurance while minimizing integration costs through a single mask change.
Implementation Method 1
Spin-transfer torque magnetoresistive random access memories (STT-MRAM) have been recognized as promising candidates since their inception. The technology is innately non-volatile, and it has been shown that STT-MRAM cells based on perpendicularly magnetized Magnetic Tunnel Junction devices (PMA-MTJs) can be written at high speed with low power.
Implementation Method 2
a magnetic random access memory (MRAM) cell incorporated in an array. More particularly, this disclosure relates to a one-time-programmable (OTP) MRAM cell embedded into an array with other multi-time-programmable MRAM types.
Data Source
Figure 1
Figure 2a~2b
Figure 2c~2d
AI summary
An integrated circuit includes a magnetic OTP memory array formed of multiple magnetic OTP memory cells having an MTJ stack with a fixed magnetic layer, a tunnel barrier insulating layer, a free magnetic layer, and a second electrode. When a voltage is applied across the magnetic OTP memory cell, the resistance of the MTJ stack and the gating transistor form a voltage divider to apply a large voltage across the MTJ stack to breakdown the tunnel barrier to short the fixed layer to the free layer. The integrated circuit has multiple MRAM arrays configured such that each of the multiple MRAM arrays have performance and density criteria that match MOS transistor based memory including SRAM, DRAM, and flash memory. The integrated circuit may include a functional logic unit connected with the magnetic OTP memory arrays and the MRAM arrays for providing digital data storage.