Delayed Wordline Activation for Memory Read Speed
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Solution Overview
Problem
The reduction in feature size of solid-state memory architecture leads to increased resistive-capacitive delay along wordlines, resulting in reduced read threshold voltage margins, especially in multi-level cell (MLC) memory architectures, causing longer read times and reduced reliability.
Innovation Solution
A revised control sequence for memory cell read operations where the selected wordline is held at ground potential while unselected wordlines are driven to normal levels, with a delayed activation of the selected wordline based on the read voltage level, allowing all wordlines to settle more quickly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If all wordlines are driven to desired values at the same time, then the read operation is simple and fast, but the resistive-capacitive delay causes increased voltage coupling between adjacent wordlines and reduced read threshold voltage margins
Solution Approach 1:
The patent applies preliminary action by first driving unselected wordlines to their desired voltage levels before driving the selected wordline. This sequence allows the unselected wordlines to settle and stabilize before the selected wordline is activated, preventing voltage coupling issues and ensuring accurate read threshold voltage measurement, thereby resolving the contradiction between speed and reliability.
2Loss of time
If the selected wordline is driven immediately, then the read time is minimized, but the far end of the selected wordline experiences significant voltage coupling from unselected wordlines
Solution Approach 1:
The patent implements preliminary action by pre-driving unselected wordlines to their target voltages before activating the selected wordline. This ensures that when the selected wordline is driven, the unselected wordlines are already stable and will not cause harmful voltage coupling at the far end of the selected wordline, thus eliminating the harmful effect while maintaining fast read time.
Solution Approach 2:
The patent applies segmentation by dividing the wordline activation process into distinct phases: first activating unselected wordlines, then activating the selected wordline after a delay. This segmentation separates the actions to prevent interference between wordlines, eliminating voltage coupling effects while preserving read speed.
3Quantity of substance
If multi-level cell architecture is used to increase capacity, then the storage density is improved, but preserving adequate voltage margins becomes more difficult and read operations become slower
Solution Approach 1:
The patent applies preliminary action by driving unselected wordlines before the selected wordline in MLC memory arrays. This sequence ensures that voltage margins are maintained during read operations, allowing accurate distinction between multiple storage levels without increasing read time, thus preserving both the high capacity benefit of MLC and fast read performance.
Data Source
AI summary
Apparatus, systems, and methods may operate to receive an external read command at a control circuit coupled to a memory array. Individual wordline activation may be delayed according to a delay period determined by a read level voltage magnitude associated with a plurality of memory cells included in the array.