Memory Array Segmentation for Localized Data Transfer
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Solution Overview
Problem
Conventional data access schemes in memory devices face challenges such as high cell-array-peripheral circuit area, high power consumption, and limited bandwidth, necessitating a novel architecture and data access method.
Innovation Solution
A memory device with a memory array divided into multiple sections, each comprising memory cells, and a data transfer circuit between sections to facilitate data movement between adjacent sections without the need for global or trans-multiple-section data lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional data access schemes are used, then data transfer between memory sections is achieved, but cell-array-peripheral circuit area is high
Solution Approach 1:
The memory array is divided into multiple memory sections, each with its own bit lines and word lines. Data transfer circuits are placed between adjacent sections to enable localized data movement, eliminating the need for global data lines that span the entire memory array. This segmentation reduces the area required for peripheral circuits while maintaining data transfer capability.
Solution Approach 2:
Data transfer circuits act as intermediary components between adjacent memory sections. These circuits include sensing buffers that sense data from bit lines in one section and drive circuits that output data to bit lines in the adjacent section. This intermediary mechanism enables efficient data transfer without requiring extensive global routing infrastructure.
2Use of energy by stationary object
If conventional data access schemes are used, then data transfer between memory sections is achieved, but power consumption is high
Solution Approach 1:
By segmenting the memory array into multiple sections with localized bit lines and word lines, the patent reduces the total length of data lines that require active driving. This segmentation decreases the capacitive loading and power consumption associated with driving long global data lines while maintaining effective data transfer between sections through localized transfer circuits.
Solution Approach 2:
The data transfer circuits serve as intermediaries that efficiently transfer data between sections using localized sensing and driving mechanisms. These circuits minimize power consumption by operating only the necessary portions of the circuitry involved in data transfer between adjacent sections, rather than activating entire global data lines.
3Productivity
If conventional data access schemes are used, then data transfer between memory sections is achieved, but bandwidth is limited
Solution Approach 1:
The memory array is segmented into multiple sections, each with its own bit lines and word lines. This segmentation enables parallel data transfer operations across different sections simultaneously, increasing the overall bandwidth. Each section can perform data transfers independently through its own localized circuits, eliminating bottlenecks associated with sequential access through global lines.
Solution Approach 2:
Data transfer circuits between adjacent memory sections function as intermediaries that enable high-speed data movement. These circuits include sensing buffers and drive circuits that can rapidly transfer data between sections, thereby increasing bandwidth. The intermediary nature of these circuits allows for efficient data propagation without the complexity of managing global data lines across the entire memory array.
Data Source
AI summary
A memory device is provided, which includes a memory array and data transfer circuits. The memory array is divided into a plurality of memory sections, and each memory section includes memory cells. Each data transfer circuit is disposed between two memory sections. A data movement occurring from all or a selected set of bit-lines or bit-line pairs between any two adjacent memory sections of the memory array is performed or to data interfaces other than the bit-lines or bit-line pairs. Data signals of all or the selected set of bit-lines or bit-line pairs of two adjacent memory sections are sensed, latched, buffered and repeated during the data movement by a data transfer circuit and data movement is sequentially performed between two memory sections to facilitate the transfer of data signals to any memory section of the memory array without the need for global or trans-multiple-section data lines.