DRAM Memory Device with Oxide Semiconductor Transistor for Leak Current Suppression
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Solution Overview
Problem
Semiconductor memory devices face challenges in data retention due to high leak currents in silicon transistors, leading to reduced data retention capability and potential malfunctions in sense amplifiers during data read operations.
Innovation Solution
The use of oxide semiconductor transistors with a specific configuration of memory cells, sense amplifiers, and potential generators that manage bit line and plate line potentials to suppress leak currents and enhance data retention, including the implementation of a potential generator that adjusts plate line potentials to minimize the impact of leak currents on data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon transistors are used in memory cells, then manufacturing process is well-established and device performance is high, but leak current is high leading to poor data retention
Solution Approach 1:
The patent changes the material parameter of the transistor channel from silicon to oxide semiconductor, which fundamentally alters the electrical characteristics. This material substitution reduces the off-state leak current while maintaining acceptable on-state performance, thereby improving data retention capability without requiring complete redesign of the memory architecture
Solution Approach 2:
The patent employs oxide semiconductor materials (such as In-Ga-Zn-O systems) that combine the advantages of both silicon-based devices and non-volatile memory characteristics. The oxide semiconductor layer is deposited over the gate electrode and forms a composite structure that provides low leak current while maintaining compatibility with existing CMOS fabrication processes
2Reliability
If plate line potential is maintained at high level, then sense amplifier operation is simplified, but leak current impact on data storage increases
Solution Approach 1:
The patent introduces dynamic potential control for the plate line, transitioning from a static high potential to a time-varying potential that changes during different operational phases. The plate line potential is raised during read operations to facilitate sense amplifier operation and lowered during write operations to minimize leak current impact, thereby adapting the potential control to operational requirements
Solution Approach 2:
The patent implements feedback control through the potential generator that monitors operational state and adjusts plate line potential accordingly. The control circuit receives signals indicating the operational phase (read or write) and dynamically adjusts the plate line potential to optimize performance for that specific operation, ensuring data storage accuracy while minimizing complexity through intelligent control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration results in improved data retention capabilities and reduced malfunctions in semiconductor memory devices by minimizing leak currents and maintaining accurate data determination in sense amplifiers, with enhanced margins for both '0' and '1' data storage cases.
Implementation Method 1
The transistor contains an oxide semiconductor. The potential generator is configured to supply the second end with a fourth potential that is different from a third potential intermediate between the first potential and the second potential.
Data Source
AI summary
A semiconductor memory device includes a memory cell that includes a capacitor including a first and second end and a first transistor. The first transistor includes a third and fourth end, is coupled to the first end at the fourth end, and contains an oxide semiconductor. A bit line is coupled to the third end. A sense amplifier is coupled to the bit line and coupled between a first node of a first potential and a second node of a second potential lower than the first potential. A potential generator is configured to supply the second end with a fourth potential that is different from a third potential intermediate between the first potential and the second potential.