Non-volatile Storage Write Modes for Noise and Stress Control
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Solution Overview
Problem
Current non-volatile semiconductor storage devices, such as NAND flash memory, face challenges in improving reliability due to noise generated during data write operations, which affects data transmission and storage efficiency.
Innovation Solution
The implementation of a non-volatile semiconductor storage device with a control circuit that performs write operations in specific modes, including a 'program pulse skip' and 'program verification skip' mode, where the application of program pulses and verification is omitted, and an automatic data pattern generation and temperature check function to enhance noise frequency and reduce operational stress on memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If program pulses are applied to memory cells during write operations, then data is written to memory cells, but noise is generated that affects reliability
Solution Approach 1:
The patent segments the write operation into two distinct modes: a first write mode that includes program pulse application for actual data writing, and a second write mode that excludes program pulse application for noise generation purposes. This segmentation allows the system to perform different functions in different modes, enabling noise generation without data corruption while maintaining data integrity when needed.
Solution Approach 2:
The patent implements dynamic switching between two write modes based on operational requirements. The control circuit can selectively activate the first write mode (with program pulses) or the second write mode (without program pulses) depending on whether data writing or noise generation is the current objective. This dynamic adaptability resolves the contradiction by allowing the system to optimize for either reliability or noise generation as needed.
2Reliability
If write operations are performed frequently to increase noise frequency, then reliability improves, but memory cells experience increased stress
Solution Approach 1:
The patent divides write operations into two categories: full write operations (first write mode) that apply program pulses and actually write data to memory cells, and partial write operations (second write mode) that charge bit lines without applying program pulses. By segmenting the operation types, the system can perform partial writes more frequently for noise generation without subjecting memory cells to the full stress of repeated program pulse application, thus improving reliability while limiting cellular stress.
Solution Approach 2:
The patent applies different operational characteristics to different parts of the write process. In the second write mode, only the bit line charging portion of the write operation is performed, while the program pulse application portion is omitted. This local differentiation allows noise generation through bit line charging without the additional stress of program pulses, enabling frequent operations that improve reliability without excessive memory cell stress.
3Measurement precision
If program verification is performed during write operations, then data accuracy is ensured, but operation time increases
Solution Approach 1:
The patent segments the write operation sequence by separating program verification from the main write process. The control circuit is configured to perform write operations without program verification in certain cases, effectively dividing the operational flow into verification-inclusive and verification-exclusive paths. This segmentation allows the system to optimize for speed when verification is not critical, reducing operation time while maintaining the option to perform verification when data accuracy is paramount.
Solution Approach 2:
The patent applies partial action by selectively omitting program verification from the write operation sequence when full verification is not required. Instead of always performing complete write operations with verification, the system can execute partial writes without verification to reduce operation time, reserving full verification processes for cases where data accuracy is critical. This partial approach balances speed and accuracy based on operational needs.
Data Source
AI summary
A non-volatile semiconductor storage device includes a memory cell array and a control circuit configured to control a data write operation for the memory cell array in a first or second write mode in response to a write command sequence. In the first write mode, the control circuit performs a first write operation, which includes an operation in which one or more bit lines are charged according to write data and an operation in which a write voltage is applied to a selected word line according to address data included in the write command sequence. In the second write mode, the control circuit performs a second write operation, which includes the operation in which the one or more bit lines are charged according to the write data and does not include the operation in which the write voltage is applied to the selected word line.