Nonvolatile Storage Device Latch Circuit Testing via Bistable Copy
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Solution Overview
Problem
Low-capacity and inexpensive OTP memory devices, such as FAMOS, face challenges in increasing reliability due to the large increase in circuit area when providing redundant memory cells, and existing methods struggle to efficiently test and rewrite values without affecting normal operation or increasing test costs.
Innovation Solution
A nonvolatile storage device with memory cells arranged in arrays, utilizing a bistable circuit connected via a switch to output values directly, allowing for testing and rewriting of latch circuit values without a dedicated input-output circuit, and using complementary memory cells to enhance data reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundant memory cells are provided to increase reliability, then data reliability is improved, but circuit area increases significantly
Solution Approach 1:
The patent makes the first output circuit serve dual purposes: it outputs values from memory cells during normal operation and outputs values from the bistable circuit during testing. By controlling the switch with row address signals, the same physical circuit path is used for both memory cell output and latch circuit output, eliminating the need for a separate dedicated output circuit for testing purposes.
Solution Approach 2:
The patent creates a functional copy of the memory cell value in the bistable circuit (latch circuit). The bistable circuit holds a copy of the selected memory cell value, which can then be tested through the first output circuit without affecting the original memory cell array structure or requiring additional test-specific hardware.
2Difficulty of detecting and measuring
If a dedicated input-output circuit is provided for testing latch circuit values, then testing capability is improved, but device complexity increases
Solution Approach 1:
The first output circuit is designed to be multi-functional, serving both normal memory cell output and latch circuit testing. The switch controlled by row address signals enables the same physical circuit to be dynamically configured for different purposes, eliminating the need for separate dedicated test output circuits and reducing overall device complexity.
Solution Approach 2:
The bistable circuit and switch are integrated into the existing memory cell structure and can be controlled using the same row address signals that are already generated during normal operation. The system uses its own existing control signals and circuit paths to perform self-testing, eliminating the need for external dedicated test equipment or additional control circuitry.
3Ease of operation
If the first output circuit is used to output the value of the selected memory cell, then normal operation is maintained, but testing of the latch circuit becomes difficult
Solution Approach 1:
The patent introduces dynamic switching capability to the first output circuit through a switch controlled by row address signals. This switch enables the output circuit to be dynamically reconfigured: during normal operation it connects to memory cells, and during testing it connects to the bistable circuit. This dynamic reconfiguration allows the same physical circuit to serve different functions at different times without compromising either normal operation or testing capability.
Solution Approach 2:
The bistable circuit is configured to hold the value of the selected memory cell before testing is needed. By using the row address signals to control both the selection of the memory cell and the subsequent switching to output mode, the system prepares the data in advance in the bistable circuit, making it ready for testing through the first output circuit without disrupting normal memory operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables direct testing and efficient rewriting of latch circuit values, reducing test costs and maintaining normal operation, while increasing data reliability without significant circuit size increases.
Implementation Method 1
a second output circuit including a bistable circuit that is electrically connected to the memory cell via a switch that is controllable by the row address and holds and outputs a value of the memory cell selected by the row address
Implementation Method 2
memory cells, each including a floating gate, are arranged in an array in a row direction and a column direction perpendicular to the row direction
Data Source
AI summary
A latch circuit that latches stored data of a nonvolatile storage device used for setting the function of a semiconductor device and adjusting the characteristics of the semiconductor device required a dedicated input-output circuit for a test of the semiconductor device. By providing a dummy storage device, it becomes possible to perform a test of the semiconductor device without providing a dedicated input-output circuit.