Non-volatile Memory Device Concurrent Pipelined Operations
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Non-volatile memory devices face significant bottlenecks due to the lengthy time required for write and erase operations, which hinder concurrent processing and lead to increased latency, limiting their application in faster and more efficient data handling.
Innovation Solution
The implementation of a non-volatile memory device with novel internal routing and buffer management systems, allowing for concurrent read and write operations by using a crossbar to route data between sense amplifiers, write data registers, and buffers, enabling parallel processing and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If iterative program-verify cycles are used to ensure correct state change, then manufacturing precision is improved, but loss of time increases significantly
Solution Approach 1:
The patent applies preliminary action by performing verify operations in parallel with subsequent program operations. Specifically, while the memory device is performing iterative program-verify cycles on a first page, it can simultaneously perform verify operations on a second page that was programmed in the meantime, thereby overlapping verification tasks with programming tasks and reducing total execution time.
Solution Approach 2:
The patent implements continuity of useful action by eliminating idle time between operations. The memory device continuously performs useful work by initiating new program operations on subsequent pages while previous verify operations are still in progress, ensuring that the processing pipeline remains full and no resources are idle during the extended program-verify cycle duration.
2Productivity
If multiple non-volatile devices or banks are used to address the time problem, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the memory array into multiple independently addressable pages within a single memory device. Each page can be programmed and verified independently, allowing the device to process multiple pages through different stages of the program-verify cycle simultaneously, achieving parallelism without requiring multiple physical devices or complex bank structures.
Solution Approach 2:
The patent implements multi-functionality by enabling a single memory device to perform multiple operations on multiple pages concurrently. The same program circuitry and verify circuitry can be applied to different pages at different times, and the device can switch between programming one page and verifying another page, making the single device capable of handling multiple operations that would traditionally require multiple devices.
3Reliability
If subsequent operations are queued until prior operations complete, then reliability is maintained, but loss of time increases due to bottlenecks
Solution Approach 1:
The patent applies preliminary action by initiating verify operations on subsequent pages before the program operations on previous pages have fully completed. The memory device can start the verify process on a second page while the program-verify cycles for a first page are still ongoing, thereby overlapping operations and reducing the total time all operations must wait for completion while maintaining proper verification of each page.
Solution Approach 2:
The patent implements dynamics by allowing the memory device to dynamically manage the state and timing of multiple page operations. The device can flexibly transition between programming and verifying different pages based on the progress of ongoing operations, dynamically allocating resources to maintain both reliability through proper verification and speed by minimizing idle wait time between operations.
Data Source
AI summary
This disclosure provides a non-volatile memory device that concurrently processes multiple page reads, erases or writes involving the same memory space. The device relies upon a crossbar and a set of page buffers that may each be dynamically assigned to each read or write request. The device also separates memory array control from IO control, such that multiple cycle state change operations can be performed while the buffers are used to transfer data into and out of the buffers along an external data bus; using this structure, the memory device can accept multiple transactions where pages can be immediately loaded into buffers and then “pipelined” either for transfer to a write data register or to an external bus as appropriate. By significantly mitigating the substantial “busy time” associated with program and erase of non-volatile memory devices, especially flash devices, this disclosure greatly expands potential application of such devices.