Memory Device Read Retry Using Premature Data Comparison

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Solution Overview

Problem

Memory devices face challenges in efficiently performing read retry operations due to erroneous read voltages, leading to uncorrectable errors and reduced data accuracy.

Innovation Solution

A memory device with a control circuit that loads premature and main data at different times, detects flip-bits between the two, and performs a read retry operation based on a read retry table with recorded levels of read voltages, allowing for optimized read voltage adjustments to improve data accuracy.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a read retry operation is performed using a fixed read voltage, then the operation is simple and fast, but data accuracy deteriorates due to erroneous read voltages causing uncorrectable errors

Engineering Contradiction:
Improvedata accuracyVSAvoidread retry operation complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by loading premature data into the page buffer before the main read operation. This premature data loading allows the system to prepare reference data in advance, which is then used for comparison during the read retry operation to detect and correct errors caused by inaccurate read voltages, thereby improving data accuracy without significantly increasing operational complexity

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback by comparing the premature data loaded in the page buffer with the main data read from the memory cell array. The detection component analyzes flip-bits between these two data sets to determine whether a read retry is necessary, and the control circuit adjusts the read voltage based on this feedback, creating a closed-loop system that continuously optimizes read accuracy

Inventive Principle:
Principle #23Feedback

2Measurement precision

If the read voltage level is adjusted to improve data accuracy, then data accuracy improves, but the operation time increases due to multiple read attempts

Engineering Contradiction:
Improvedata accuracyVSAvoidread operation time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

By loading premature data into the page buffer before the main read operation, the system prepares reference data in advance. This allows for rapid comparison during the read retry operation, enabling quick detection of read errors and minimizing the time penalty associated with retry operations, thus reducing overall data access time while maintaining high accuracy

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent replaces the traditional mechanical retry approach (repeated read attempts with fixed voltage) with an electronic comparison mechanism. The detection component electronically compares premature and main data to identify flip-bits, and the control circuit electronically adjusts the read voltage based on this comparison, substituting mechanical retry cycles with faster electronic detection and adjustment processes

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS10553296B2Memory device and operating method thereof
Publication Date: 2020.02.04 SK HYNIX INC
  • US10553296B2 patent drawing
  • US10553296B2 patent drawing
  • US10553296B2 patent drawing

AI summary

A memory device includes a memory cell array including a plurality of memory cells coupled to a plurality of word lines and a plurality of bit lines; a read/write circuit including a plurality of page buffers coupled to the plurality of bit lines; a power supply circuit suitable for generating voltages to be applied to the memory cell array and the read/write circuit; and a control circuit suitable for receiving a read command and an address signal from an external device, and controlling the memory cell array, the read/write circuit and the power supply circuit based on the read command and the address signal.