OTP Fuse Bit Self-Sensing Mechanism for CMOS Integration
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Solution Overview
Problem
Existing non-volatile memory technologies, such as flash EEPROM and antifuse devices, lag behind advanced CMOS logic processes, requiring more mask steps and being more expensive, due to complex high-voltage generation circuits and structures like floating gates and triple wells, which complicates their fabrication and increases costs.
Innovation Solution
The development of one-time programmable (OTP) non-volatile fuse memory cells that use standard CMOS processes, with a self-sensing mechanism that allows programming and reading without additional masking, utilizing a select transistor and a programming transistor to break down the fuse and sense current for data content, optimizing for low bit count applications and reducing the need for decoding or addressing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If standard CMOS processes are used for OTP fuse memory cells, then manufacturing cost and fabrication complexity are reduced, but the memory cells require optimization for low bit count applications which limits versatility
Solution Approach 1:
The patent changes the operational parameters of the fuse memory cell by using self-sensing mechanisms and specific transistor configurations (select transistor and programming transistor) that enable standard CMOS compatibility. The fuse bit is designed to operate at standard CMOS voltages and be read through current sensing without requiring high-voltage generation circuits, thus resolving the contradiction between ease of manufacture and versatility
2Device complexity
If self-sensing mechanism is implemented, then sense amplifiers are eliminated reducing device complexity, but programming and reading require precise current sensing which increases manufacturing precision requirements
Solution Approach 1:
The fuse memory cell implements a self-sensing mechanism where the programmed fuse bit itself provides the sensing function through its resistance state. The select transistor and programming transistor configuration allows the cell to sense its own state through current flow without requiring external sense amplifiers. This eliminates complex sensing circuitry while the precision is achieved through the inherent electrical characteristics of the fuse and transistor combination, resolving the contradiction between device complexity and manufacturing precision
3Reliability
If fuse breakdown is used for programming, then non-volatile storage is achieved, but high voltage is required for programming which increases device complexity
Solution Approach 1:
The patent extracts the high-voltage generation circuits from the memory cell structure, using external high-voltage sources for programming while the memory cell itself operates at standard CMOS voltages for reading and normal operation. The fuse breakdown mechanism is retained for reliable non-volatile storage, but the complexity of on-chip high-voltage generation is removed, resolving the contradiction between reliability and device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The OTP fuse memory cells occupy less area, are optimized for low bit count applications, and can be used for code storage and ID purposes, offering efficient and cost-effective solutions by leveraging standard CMOS processes and eliminating the need for sense amplifiers, thus bridging the gap with advanced CMOS logic processes.
Implementation Method 1
utilizing a select transistor and a programming transistor to break down the fuse
Implementation Method 2
sense current for data content
Data Source
Figure 1~5A
Figure 5B~6
Figure 7~8
AI summary
One-time programmable (OTP) nonvolatile fuse memory cells are disclosed that do not require decoding or addressing for reading their data content. Each fuse memory cell has its content latched at its output and available at all times and can be used, for example, for code storage memories, serial configuration memories, and as individual fuse bits for ID (identification), trimming, and other post-fabrication System-on-Chip (SoC) customization needs. Means are also provided for temporary data storage for design testing, etc. In alternative embodiments, using two differentially programmed fuses in a single memory cell, the selection and programming circuitry are merged.