Semiconductor Memory Device Shared Row Decoder Architecture
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor memory devices face challenges in efficiently managing the increased chip area and processing capability due to the separate coupling of word lines to the row decoder, leading to area expansion and potential disturbances during write and read operations.
Innovation Solution
The semiconductor memory device employs a configuration where multiple memory cell arrays are stacked with commonly coupled word lines and bit lines, allowing for simultaneous selection and processing of cell units, thereby reducing the number of coupled word lines and bit lines, and minimizing area expansion and disturbance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If word lines are separately coupled to the row decoder in each memory cell array, then each array can be independently accessed, but the chip area increases and processing efficiency decreases
Solution Approach 1:
The patent merges the word line coupling resources by implementing a shared row decoder that serves multiple memory cell arrays (e.g., four arrays). Instead of providing separate word line couplings to each array, the invention combines the coupling paths, allowing the same row decoder to sequentially or simultaneously manage word lines across different arrays through multiplexing techniques.
Solution Approach 2:
The row decoder is designed with multi-functionality to handle word line decoding for multiple memory cell arrays. A single row decoder unit performs the decoding function universally across all connected arrays, eliminating the need for dedicated decoders for each array and thereby reducing the overall chip area while maintaining independent array access capability.
2Adaptability or versatility
If word lines are separately coupled to the row decoder, then array independence is maintained, but processing capability and speed are reduced
Solution Approach 1:
The shared row decoder enables continuous operation across multiple memory cell arrays by eliminating idle time between array accesses. While one array is being accessed, the decoder can prepare decoding signals for the next array, ensuring that the useful action of data processing continues without interruption, thereby enhancing overall processing capability.
Solution Approach 2:
The invention introduces dynamic resource allocation where the row decoder can be dynamically assigned to different memory cell arrays based on access requirements. This dynamic sharing allows the system to optimize processing speed by allocating decoder resources to the array that needs access at any given moment, improving overall productivity while maintaining array independence.
3Reliability
If multiple memory cell arrays are processed separately, then data integrity is maintained, but disturbances occur during write and read operations
Solution Approach 1:
The shared row decoder acts as an intermediary that coordinates access to multiple memory cell arrays, managing the timing and sequencing of read and write operations. By controlling the decoding signals centrally, the intermediary decoder ensures that operations on different arrays are synchronized properly, preventing disturbances while maintaining data integrity across all arrays.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes: a first memory cell array; a second memory cell array arranged above the first memory cell array; a third memory cell array arranged adjacent to the first memory cell array; a fourth memory cell array arranged above the third memory cell array and arranged adjacent to the second memory cell array; a first word line coupled to the first memory cell array and the second memory cell array; a second word line coupled to the third memory cell array and the fourth memory cell array; a first bit line coupled to the first memory cell array and the fourth memory cell array; and a second bit line coupled to the second memory cell array and the third memory cell array.