Nonvolatile Memory Page Buffer Grouping for Partial Access
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Solution Overview
Problem
Existing memory devices face challenges in optimizing access time when accessing data in units smaller than a page, as they are not efficiently designed to handle partial page access operations.
Innovation Solution
A memory device with a memory cell array and multiple page buffers, equipped with an enable control circuit that divides the page buffers into groups and selectively enables them during specific operation modes to adjust the access time based on the size of data being accessed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If all page buffers are enabled simultaneously for partial page access, then access speed is improved, but power consumption and circuit complexity increase
Solution Approach 1:
The page buffers are divided into multiple groups (first group and second group), allowing selective enabling of only the necessary groups for partial page access. This segmentation enables the circuit to activate fewer buffers when accessing data smaller than a full page, thereby reducing circuit complexity and power consumption while maintaining fast access speed.
Solution Approach 2:
Instead of enabling all page buffers simultaneously, the patent enables only the necessary L groups (where L ≤ P) required for the specific access operation. This partial action approach activates only the minimal necessary circuit resources, reducing overall circuit complexity and power consumption while still achieving the required access speed for the given data size.
2Loss of time
If all page buffers are enabled simultaneously, then access time is reduced, but power consumption increases
Solution Approach 1:
By segmenting page buffers into groups and selectively enabling only the necessary groups for the current access operation, the patent reduces the number of active circuits, thereby lowering power consumption while maintaining fast access time through parallel operation of the enabled groups.
Solution Approach 2:
The patent dynamically changes the number of enabled page buffer groups based on the access requirements. When accessing data smaller than a page, only L groups are enabled instead of all P groups, optimizing the balance between access time and power consumption by adjusting the operational parameters to match the actual data access needs.
3Use of energy by moving object
If page buffers are sequentially enabled, then power consumption is reduced, but access time increases
Solution Approach 1:
The patent segments page buffers into multiple groups that can be enabled in parallel within each group. This allows the system to reduce power consumption by activating fewer groups while maintaining fast access time through simultaneous operation of buffers within each enabled group, avoiding the sequential enabling bottleneck.
Solution Approach 2:
The patent enables only the necessary L groups of page buffers rather than all P groups, achieving partial action that reduces power consumption. Within these L groups, buffers operate in parallel, ensuring that access time remains short despite enabling fewer groups, thus resolving the trade-off between power consumption and access time.
4Adaptability or versatility
If the memory device is designed for full page access, then circuit simplicity is maintained, but flexibility for partial page access is reduced
Solution Approach 1:
The enable control circuit divides page buffers into groups and implements control logic to selectively enable specific groups based on access requirements. This segmentation approach provides flexibility for partial page access by allowing different combinations of groups to be activated, while the control circuit remains relatively simple by using systematic grouping and enable signals.
Solution Approach 2:
The patent implements dynamic control of page buffer groups through the enable control circuit, which can adaptively enable different numbers and combinations of groups based on the specific access operation. This dynamic capability provides versatility for various access sizes without requiring a completely complex control circuit, as the grouping structure enables flexible configuration through systematic enable signals.
Data Source
AI summary
A memory device including a memory cell array having multiple memory cells, multiple page buffers connected to the memory cells, and an enable control circuit configured to divide the page buffers into P groups, sequentially enable L groups among the P groups during an entry interval of an operation mode, and adjust a length of the entry interval of the operation mode based on a value of L, wherein P is a natural number greater than or equal to 2, and L is a natural number greater than or equal to 1 and less than or equal to P.