Dynamic Target Erase Level Adjustment in Semiconductor Memory
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Solution Overview
Problem
As the erase-program cycling number increases in semiconductor memory devices, physical and electrical degradation occurs, making it difficult to reduce threshold voltages to a target level, requiring higher erase voltages and increasing operation time, which can lead to over-erase and stress on the device.
Innovation Solution
A method and semiconductor memory device that dynamically adjust the target erase level based on the erase-program cycling number by maintaining or incrementally increasing the target level, using a spare block to store cycling data and controlling the erase verify voltage to prevent over-erase and reduce stress, allowing for efficient threshold voltage reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a fixed target erase level is used for all erase operations, then the erase operation can be completed quickly when the device is new, but over-erase operations occur and stress increases when the erase-program cycling number is high
Solution Approach 1:
The patent applies dynamics by making the target erase level adjustable rather than fixed. The control circuit dynamically changes the target erase level based on the erase-program cycling number stored in the spare block. When the cycling number is low, a lower target erase level is used for faster erasure; when the cycling number is high, a higher target erase level is used to prevent over-erase and reduce stress, thus resolving the contradiction between speed and reliability
Solution Approach 2:
The patent changes the parameter of target erase level based on the erase-program cycling number. By storing the cycling number in the spare block and using it to determine the appropriate target erase level, the system adapts the erase parameters to the device's current state, preventing over-erase operations while maintaining efficient erasure when appropriate
2Reliability
If higher erase voltage is applied to reduce threshold voltages to target level, then erase operation can be completed for degraded devices, but operation time increases and stress on device increases
Solution Approach 1:
The patent changes the target erase level parameter based on the erase-program cycling number rather than always applying higher erase voltage. This allows the system to achieve complete erasure for degraded devices by adjusting the target level appropriately, rather than increasing voltage, thus reducing operation time and stress while maintaining erase completeness
3Reliability
If erase voltage is gradually increased to reduce threshold voltages to target level, then all memory cells can be erased, but operation time increases and device stress increases
Solution Approach 1:
The patent applies dynamics by dynamically setting the target erase level based on the erase-program cycling number. This allows the system to determine the appropriate erasure criterion in advance, avoiding prolonged incremental voltage increases and reducing operation duration while ensuring complete erasure of all memory cells
Data Source
AI summary
A method of operating a semiconductor memory device includes checking an erase-program cycling number, setting a target erase level to be maintained when the erase-program cycling number is less than a predetermined critical number, and setting the target erase level to be increased when the erase-program cycling number is greater than or equal to the predetermined critical number, and performing an erase operation so that threshold voltages of selected memory cells are less than the set target erase level.