NAND Flash Memory Register Sharing for Set Feature Command Area Reduction
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Solution Overview
Problem
As NAND flash memory capacity increases, the number of setting-change allowable states also increases, leading to a need for more registers, which in turn requires a larger memory chip area to store information on setting changes instructed by a set feature command sequence.
Innovation Solution
A semiconductor memory device is designed with a plurality of first latch circuits that latch setting-data at different timings, corresponding hold circuits to store this data, and an address decoder to specify the destination for holding data, simplifying the circuit configuration by sharing latch circuits across holding parts, reducing the overall circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of registers is increased to store setting-change information for more states, then the memory capacity and number of setting-change allowable states increase, but the memory chip area increases
Solution Approach 1:
The patent merges the functionality of multiple registers into a single register by using time-division multiplexing. The set feature command sequence operates in multiple phases (first phase and second phase), where different settings are stored in the same register at different times. This eliminates the need for separate registers for each setting, thereby reducing the memory chip area while maintaining the ability to store multiple setting-change information.
Solution Approach 2:
The patent segments the set feature command sequence into multiple phases: a first phase for setting certain memory internal states and a second phase for setting other memory internal states. This temporal segmentation allows a single register to handle multiple settings sequentially, resolving the contradiction between supporting more settings and using less chip area.
2Adaptability or versatility
If the number of registers is increased to store setting-change information, then more setting-change allowable states are supported, but the circuit complexity increases
Solution Approach 1:
The patent combines multiple register functions into a single register by implementing time-division multiplexing through phased command sequences. The same register is reused for different settings in different phases, reducing the total number of registers required while maintaining support for multiple setting-change states.
Solution Approach 2:
The single register is designed to serve multiple functions by storing different setting-change information at different times during the set feature command sequence. This multi-functionality eliminates the need for dedicated registers for each setting, thereby reducing device complexity while maintaining versatility.
Data Source
AI summary
A semiconductor memory device according to an embodiment is provided with a plurality of first latch circuits that latch setting-data at different timings, a plurality of hold circuits provided corresponding to the respective plurality of first latch circuits, each holding data latched by the corresponding first latch circuit, and an address decoder that decodes an address that specifies a destination to hold data. Each of the plurality of hold circuits has one or more holding parts that hold data latched by the corresponding first latch circuit based on a decode signal decoded by the address decoder.