Semiconductor Memory Program Disturb Mitigation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor memory devices face challenges in maintaining data reliability due to the program disturb phenomenon, which increases threshold voltage distribution in memory cells after a program operation, affecting the erase state's threshold voltage distribution.
Innovation Solution
A semiconductor memory system that includes a memory block with a peripheral circuit and control logic to perform program and erase operations, where the control logic decreases threshold voltages of memory cells in the erase state by applying an erase voltage to bit lines based on data stored in page buffers, thereby selectively erasing only memory cells in the erase state after a program operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a program operation is performed on memory cells, then data is programmed into the memory cells, but the threshold voltage distribution of memory cells in the erase state increases due to program disturb phenomenon
Solution Approach 1:
The patent applies a preliminary erase operation to memory cells that are in the erase state before completing the program operation. This preliminary action reduces the threshold voltage of affected memory cells proactively, preventing the program disturb phenomenon from degrading the threshold voltage distribution. By performing this erase operation in advance rather than waiting for degradation to occur, the system maintains reliable threshold voltage distribution while enabling continuous program operations.
2Reliability
If the threshold voltage distribution of erase state memory cells is reduced by applying erase voltage, then data reliability is improved, but additional erase operations increase operation time
Solution Approach 1:
The patent applies erase voltage selectively to only those memory cells that are in the erase state and affected by the program disturb phenomenon, rather than performing a full erase operation on all memory cells in the block. This localized approach reduces the threshold voltage of affected cells to improve data reliability while minimizing the additional operation time required. The control logic identifies and targets only the specific memory cells needing correction.
Solution Approach 2:
The patent performs a partial erase operation that targets only the subset of memory cells requiring threshold voltage reduction, rather than completing a full erase cycle. This partial action is sufficient to correct the program disturb effect on affected cells without the time penalty of a complete erase operation, thereby improving data reliability with minimal time overhead.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves data reliability by reducing the threshold voltage distribution of memory cells in the erase state, ensuring that threshold voltages remain lower than the target voltage, thus enhancing the overall performance and stability of semiconductor memory devices.
Implementation Method 1
the control logic decreases threshold voltages of memory cells corresponding to an erase state among a plurality of memory cells included in the selected page in the erase operation
Implementation Method 2
perform a program operation on a plurality of memory cells included in a selected page among a plurality of pages by applying a program voltage to a word line corresponding to the selected page
Data Source
AI summary
There are provided a semiconductor memory and an operating method thereof. The semiconductor memory includes a memory block including a plurality of pages, a peripheral circuit for performing a program operation and an erase operation on a selected page among the plurality of pages, and a control logic for controlling the peripheral circuit to perform the program operation and the erase operation. The control logic decreases threshold voltages of memory cells corresponding to an erase state among a plurality of memory cells included in the selected page in the erase operation.