Shared Bit Line Source Line Resistive Memory Structure
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Solution Overview
Problem
Resistive sense memory arrays face challenges with slow access speed and integration difficulties due to high current requirements for writing, voltage drops on bit and source lines, and increased resistivity as array density increases, limiting their scalability and performance.
Innovation Solution
A resistive sense memory array structure with shared bit lines and source lines, where a single bit line and source line are used for multiple memory elements, reducing resistivity and enabling faster access speeds and higher density by using semiconductor transistors and a specific biasing method to prevent current leakage through adjacent pathways.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If each memory element has its own bit line and source line, then writing current can be applied to each element, but voltage drop increases and resistivity increases as array size and density increase
Solution Approach 1:
The patent merges multiple bit lines into a shared bit line and multiple source lines into a shared source line. Specifically, a first bit line is shared between a first memory element and a second memory element, and a first source line is shared between a first memory element and a second memory element. This combining approach reduces the total number of bit lines and source lines, thereby reducing overall resistivity and voltage drop in the array while maintaining the ability to write to individual elements through selective transistor control.
2Quantity of substance
If array density increases, then storage capacity increases, but bit line width becomes narrower and resistivity increases
Solution Approach 1:
By combining multiple bit lines into a single shared bit line, the patent effectively increases the functional width of the bit line without physically increasing the width of individual metal traces. The shared bit line carries current for multiple memory elements, reducing the current density and resistive heating in each individual bit line path.
Solution Approach 2:
The shared bit line and source line structure makes these conductors universal resources that serve multiple memory elements. A single bit line can be used to access multiple memory elements at different times, and the biasing scheme enables the same physical infrastructure to support both read and write operations across the array.
3Quantity of substance
If array size becomes larger, then storage capacity increases, but voltage drop on bit line and source line increases
Solution Approach 1:
The patent reduces the total length and number of bit lines and source lines by combining multiple lines into shared lines. This merging reduces the overall resistive path in the array, thereby reducing voltage drop as the array size increases. The shared structure allows larger arrays to be built without proportionally increasing the voltage drop that would occur with individually dedicated lines for each element.
Data Source
AI summary
A resistive sense memory apparatus includes a first semiconductor transistor having a first contact electrically connected to a first source line and a second contact electrically connected to a first resistive sense memory element and a second semiconductor transistor having a first contact electrically connected to a second source line and a second contact electrically connected to a second resistive sense memory element. A bit line is electrically connected to the first resistive sense memory element and the second resistive sense memory element.