Semiconductor Memory Voltage Skew Compensation via Feedback

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Solution Overview

Problem

Semiconductor memory apparatuses face challenges in maintaining a constant target voltage level due to process variations, geometrical effects, and physical position influences, leading to voltage skew issues that can cause circuit malfunctions.

Innovation Solution

A semiconductor memory apparatus comprising a skew monitoring unit, voltage sensing unit, coding unit, and internal voltage regulation unit that monitor and regulate the voltage characteristics of MOS transistors to provide a stable internal voltage, compensating for voltage skew by adjusting the internal bias voltage based on sensing results.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a constant target voltage is set for MOS transistors, then circuit reliability is improved, but voltage skew occurs due to process variation and physical position effects

Engineering Contradiction:
Improvecircuit reliabilityVSAvoidvoltage level precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent implements a feedback mechanism where the actual voltage characteristics of MOS transistors are monitored and used to adjust the target voltage. The skew monitoring unit detects voltage deviations caused by process variation and physical position effects, and the target voltage is dynamically adjusted based on this feedback to compensate for the deviations, thereby maintaining circuit reliability while accounting for manufacturing variations.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent changes the target voltage parameter dynamically based on the monitored voltage characteristics of MOS transistors. Instead of using a fixed target voltage, the system adjusts the target voltage level according to the actual transistor performance, which varies due to process variation and physical position. This parameter adaptation resolves the contradiction by allowing the target voltage to track actual transistor characteristics.

Inventive Principle:
Principle #35Parameter changes

2Adaptability or versatility

If various voltage levels are applied to different word lines, then memory operation flexibility is improved, but voltage skew and circuit malfunction risk increase

Engineering Contradiction:
Improvememory operation flexibilityVSAvoidcircuit reliability
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent applies local quality by adjusting the target voltage for each word line based on its specific characteristics and position. Different word lines may have different voltage requirements due to their physical location and process variation, so the system tailors the voltage level locally for each word line rather than applying a uniform voltage, thereby maintaining both flexibility and reliability.

Inventive Principle:
Principle #3Local quality

3Stability of the object's composition

If target voltage is adjusted to compensate for process variation, then voltage stability is improved, but additional monitoring and control circuits are required

Engineering Contradiction:
Improvevoltage stabilityVSAvoidcontrol circuit complexity
Core Design Contradiction:
Stability of the object's compositionVSDevice complexity

Solution Approach 1:

The patent implements self-service by using the voltage characteristics of the MOS transistors themselves to generate the correction information. The skew monitoring unit utilizes the actual voltage drops across the transistors during normal operation to detect deviations, and this information is fed back to adjust the target voltage. The system serves itself by using its own operational characteristics as the basis for correction, minimizing the need for external calibration equipment or complex control mechanisms.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS8665656B2Semiconductor memory apparatus and method for controlling the same
Publication Date: 2014.03.04 SK HYNIX INC
  • US8665656B2 patent drawing
  • US8665656B2 patent drawing
  • US8665656B2 patent drawing

AI summary

A semiconductor memory apparatus includes: a skew monitoring unit configured to receive a reference voltage and monitor a voltage characteristic of a corresponding MOS transistor; a voltage sensing unit configured to provide a sensing voltage corresponding to the monitoring result of the voltage characteristic; a coding unit configured to multiplex an output signal of the voltage sensing unit and provide a skew control signal; and an internal voltage regulation unit configured to provide an internal voltage by regulating an internal bias voltage in response to the skew control signal.