Semiconductor Memory Word Line Decoding for Non-Power-of-2 Cell Blocks
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Solution Overview
Problem
In semiconductor memory devices with non-power-of-2 word lines per cell block, the selection of word lines becomes complex, leading to increased delay times and larger decoding circuit areas, which degrade AC characteristics and current consumption.
Innovation Solution
A semiconductor memory device with a block decoding unit, block information address generating unit, and word line driving unit that simplifies the selection process by incorporating cell block selection information into the address used for word line selection, reducing delay times and decoding circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of word lines per cell block is not a power of 2 (e.g., 384), then the memory device can store more data per block, but the word line selection becomes complex and decoding circuit area increases
Solution Approach 1:
The patent divides the word line selection process into two independent stages: cell block selection (using addresses X7:11) and word line selection within the selected block (using addresses X0:6). This segmentation allows each stage to operate independently with simple decoding logic, avoiding the complexity of decoding all 384 word lines simultaneously while maintaining the ability to access any word line in the block.
Solution Approach 2:
The patent introduces a hierarchical address structure that adds a dimension of cell block selection before word line selection. By first selecting the cell block using higher-order addresses (X7:11) and then selecting the word line within that block using lower-order addresses (X0:6), the system transforms a complex one-to-many mapping problem into a simpler multi-stage process.
2Quantity of substance
If the number of word lines per cell block is not a power of 2, then more data can be stored, but decoding circuit area and current consumption increase
Solution Approach 1:
The decoding circuit is segmented into two independent decoders: a first decoder for cell block selection (receiving addresses X7:11) and a second decoder for word line selection within the block (receiving addresses X0:6). This segmentation reduces the area of each individual decoder compared to a single decoder handling all 384 word lines, while collectively providing the full addressing capability.
Solution Approach 2:
The first decoder serves multiple functions: it selects the cell block and simultaneously provides selection signals to multiple second decoders within that block. This multi-functionality reduces the overall circuit area by avoiding redundant decoding logic across different cell blocks.
3Quantity of substance
If the number of word lines per cell block is not a power of 2, then data capacity increases, but word line selection delay time increases
Solution Approach 1:
The word line selection process is segmented into two sequential stages with independent timing: first cell block selection (using addresses X7:11), then word line selection within the block (using addresses X0:6). This segmentation allows each stage to complete its decoding independently, reducing the total delay time compared to decoding all 384 word lines simultaneously.
Solution Approach 2:
The cell block selection is performed as a preliminary action before word line selection. By first identifying which cell block is active using addresses X7:11, the system prepares the selection path in advance, allowing the subsequent word line selection (using addresses X0:6) to proceed more efficiently without requiring full decoding of all word lines.
Data Source
AI summary
A semiconductor memory device having a plurality of cell blocks includes: a block decoding unit configured to decode an input address for selecting a corresponding cell block to generate a block selection signal; a block information address generating unit configured to perform a logic operation on the block selection signal and an assignment address for selecting a word line to be activated within the corresponding cell block to generate a block information address activated only when the corresponding cell block is selected; and a word line driving unit configured to select a word line in response to the block information address.