Semiconductor Memory Device Bit Line Voltage Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor memory devices face challenges in optimizing read operation speed and current consumption during data reading in NAND-type flash memory systems, with existing methods either resulting in slow read speeds or high current consumption.
Innovation Solution
The semiconductor memory device employs a two-time reading scheme with a sense amplifier module that applies pre-charge voltage and source line voltage management, using a voltage SRCGND intermediate between the pre-charge and source line voltages to stabilize bit line voltage and current, reducing current consumption while maintaining high read speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If lockout method is used to reduce current consumption, then current consumption is reduced, but read operation speed becomes slow
Solution Approach 1:
The patent dynamically adjusts the bit line voltage to an intermediate level (SRCGND) between pre-charge voltage and ground during the read operation. This dynamic voltage adjustment allows the system to maintain faster read speeds while reducing current consumption compared to traditional lockout methods that hold the bit line at ground potential.
Solution Approach 2:
The patent changes the voltage parameter of the bit line from binary states (pre-charge voltage or ground) to a three-state system including an intermediate voltage (SRCGND). This parameter change enables optimized current consumption while maintaining read operation speed by stabilizing the bit line at a voltage level that reduces current flow without completely discharging it.
2Speed
If no-lockout method is used to increase read speed, then read operation speed is improved, but current consumption increases
Solution Approach 1:
The patent introduces an intermediate voltage level (SRCGND) as a mediator between the pre-charge voltage and ground potential. This intermediary voltage state allows the bit line to maintain sufficient voltage for fast read operations while reducing the voltage differential that drives current consumption, thus balancing speed and energy efficiency.
3Use of energy by moving object
If bit line voltage is stabilized at intermediate level, then current consumption is reduced and read speed is maintained, but voltage stability control complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-establishing the intermediate voltage level (SRCGND) before the read operation begins and maintaining it throughout the operation. This preliminary voltage setup simplifies the control logic compared to dynamic adjustments during the operation, as the voltage level is predetermined and maintained by control circuitry rather than requiring complex real-time adjustments.
Data Source
AI summary
A semiconductor memory device includes a memory cell, a bit line electrically connected to a first end of the memory cell, a source line electrically connected to a second end of the memory cell, a sense amplifier electrically connected to the bit line, and a controller configured to perform a read operation including first and second read operations on the memory cell. During the first read operation, a pre-charge voltage is applied to the bit line and a source line voltage lower than the pre-charge voltage is applied to the source line, and during the second read operation, a first voltage that is greater than the source line voltage and less than the pre-charge voltage is applied to the bit line.