Block Decoder Metal Line Area Reduction via Signal Extraction
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Solution Overview
Problem
Existing block decoders in semiconductor memory devices require significant area for metal lines to handle high voltage address signals, limiting the integration density and efficiency of flash memory devices.
Innovation Solution
A block decoder design utilizing a depletion high voltage NMOS transistor and a high voltage PMOS transistor to generate a block selection signal, reducing the area occupied by metal lines by controlling the control and discharge signals with a time lag, and using these transistors to manage the block selection signal generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If traditional block decoder circuitry is used to handle high voltage address signals, then the block selection function is achieved, but the area occupied by metal lines increases significantly
Solution Approach 1:
The patent extracts the high voltage signal handling function from the traditional block decoder circuitry and relocates it to the bit line driver circuit. Specifically, the bit line driver receives and amplifies high voltage address signals directly, eliminating the need for separate metal lines to transport these signals to a dedicated block decoder, thereby reducing metal line area while maintaining block selection capability
Solution Approach 2:
The bit line driver is designed to perform multiple functions: it not only drives the bit lines for read operations but also handles block selection for high voltage address signals. This multi-functionality consolidates circuitry that would traditionally require separate dedicated components and metal lines, reducing overall area while maintaining ease of manufacture
2Area of stationary object
If high voltage address signals are routed through dedicated metal lines to the block decoder, then block selection accuracy is maintained, but the device area increases
Solution Approach 1:
The patent introduces the bit line driver as an intermediary component that receives high voltage address signals and performs the selection function. This intermediary handles the signal amplification and block selection logic locally, eliminating the need for long dedicated metal lines while maintaining selection accuracy through the driver's internal circuit design
Solution Approach 2:
The patent transitions from a planar layout requiring extensive metal lines to a vertical integration approach where the bit line driver is positioned adjacent to the memory cell array. This dimensional reorganization allows signals to be handled locally without requiring long horizontal metal line routes, reducing area while preserving selection precision
Data Source
AI summary
A block decoder of a semiconductor memory device includes a control signal generation circuit configured to generate an initial control signal and a block selection control signal in response to memory block selection addresses, an output node control circuit configured to set up an initial voltage of an output node in response to the initial control signal, and a block selection signal generation circuit configured to generate a block selection signal by raising a potential of the output node in response to the block selection control signal and the initial voltage of the output node.