Block-Based DVS Wafer Testing Using Temperature-Correlated Voltage

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Solution Overview

Problem

Current DVS tests apply a fixed voltage to all blocks of a die, failing to optimize the dynamic voltage stress (DVS) conditions, which affects wafer yield and increases defect parts per million (DPPM).

Innovation Solution

A method and system for optimizing DVS conditions by selecting a testing block, acquiring measurement and predict temperatures, configuring a tip burnt block temperature, determining a DVS block target temperature, and generating a block-specific voltage using a correlation table and machine learning model.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a fixed DVS voltage is applied to all blocks of a die, then the testing process is simple and fast, but the DVS conditions are not optimized and DPPM increases

Engineering Contradiction:

Improvewafer reliabilityVSAvoidDVS testing complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The die is divided into multiple blocks, and each block is assigned a specific temperature range based on its characteristics. The processor selectively applies DVS voltage to individual blocks rather than treating the entire die uniformly, enabling optimized stress conditions for each block while maintaining manageable testing complexity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different temperature ranges are assigned to different blocks within the die based on their specific characteristics. The DVS voltage is applied locally to specific blocks rather than uniformly across the entire die, allowing each block to receive optimized stress conditions tailored to its local requirements.

Inventive Principle:

Principle #3Local quality

2Reliability

If a fixed DVS voltage is applied to all blocks of a die, then the testing process is simple, but the DVS failure rate cannot be reduced effectively

Engineering Contradiction:

ImproveDVS failure rate reductionVSAvoidDVS condition optimization precision

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The DVS testing process transitions from a static, uniform voltage application to a dynamic, block-specific approach. The processor dynamically determines which blocks require DVS voltage based on their temperature ranges and characteristics, and applies voltage with precise control over which blocks are stressed, thereby reducing failure rates while maintaining manufacturing precision.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the parameters of DVS testing by introducing block-specific temperature ranges and selectively applying voltage based on these parameters. Instead of using a single fixed voltage for all blocks, the system adjusts voltage application parameters according to each block's characteristics, enabling both failure rate reduction and precise condition optimization.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS12480987B2Dynamic voltage stress condition optimization method and dynamic voltage stress condition optimization system capable of performing block-based dynamic voltage stress wafer testing process

Publication Date: 2025.11.25 MEDIATEK INC

AI summary

A dynamic voltage stress (DVS) condition optimization includes selecting a testing block from a plurality of blocks in a die of a wafer, acquiring a plurality of testing block measurement temperatures of the testing block when the testing block is processed by a DVS testing flow, acquiring a correlation table of the plurality of testing block measurement temperatures and a plurality of DVS block predict temperatures of the testing block, configuring a tip burnt block temperature according to the testing block measurement temperatures, determining a DVS block target temperature selected from the DVS block predict temperatures according to the correlation table and the tip burnt block temperature, and generating a DVS block voltage for applying to the testing block in the die of the wafer according to the DVS block target temperature.