Context-Aware Block IR Drop Analysis for VLSI Design
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Solution Overview
Problem
The traditional hierarchical design flow for VLSI circuits is inefficient in analyzing and fixing rail voltage drops (IR drops) due to the lengthy and time-consuming full-chip analysis process, which hinders the validation of fixes in block designs, leading to prolonged design cycles.
Innovation Solution
A context-aware block design IR-drop fixing flow is introduced, where block-contexts are created to simulate external circumstances, allowing for block-level IR drop analysis that mimics full-chip analysis, reducing the need for repeated full-chip analysis and accelerating the fixing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If full-chip analysis is performed for IR drop validation, then analysis accuracy is improved, but analysis time increases significantly
Solution Approach 1:
The full-chip analysis is segmented into block-level analysis units. Each block is analyzed independently with its own IR drop calculations, allowing parallel processing and significantly reducing total analysis time while maintaining accuracy through localized context-aware modeling.
Solution Approach 2:
Context-aware block models serve as intermediaries between detailed block designs and full-chip analysis. These models capture essential electrical characteristics and boundary conditions, enabling accurate block-level validation without requiring complete full-chip analysis for every validation iteration.
2Productivity
If block-level analysis is performed without full-chip context, then analysis speed is improved, but analysis accuracy deteriorates
Solution Approach 1:
The context-aware block model incorporates local electrical characteristics and boundary conditions specific to each block's position and connectivity in the full-chip. This localized quality information is integrated into the block-level analysis, maintaining accuracy while enabling faster block-level validation.
3Reliability
If repeated full-chip analysis is performed to validate fixes, then validation reliability is improved, but design cycle time increases
Solution Approach 1:
Block-level context-aware analysis is performed as a preliminary validation step before committing to full-chip analysis. This preliminary action identifies and validates fixes at the block level, reducing the need for repeated full-chip analysis and shortening the overall design cycle while maintaining validation reliability.
Data Source
AI summary
A system is disclosed that includes a memory and a processor to perform operations, including analyzing rail voltage drop for a full-chip to identify an IR drop violation in a block design of the full-chip. The operations include performing a block-level rail voltage drop analysis for the block design and generating a revised block design corresponding to the block design in which the IR drop violation is identified. The operations include performing a block-level rail voltage drop analysis on the revised block design to verify that the IR drop violation is fixed and integrating the revised block design into the full-chip to replace the block design upon verifying that the IR drop violation is fixed. The operations include performing the rail voltage drop analysis for the full-chip comprising the revised block design.