Block-Level IO Timing Model for Circuit Hold Violation Correction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Timing violations in circuit design, such as hold violations, are typically corrected during final stages before tape-out, leading to increased design time due to multiple iterations of flat timing model-based corrections.
Innovation Solution
A method and system for correcting timing violations by constructing block-level IO timing models, detecting paths between interconnected circuit blocks, and adding delay elements to ensure delays are within a predetermined target range, even in early design stages, using static timing analysis and clock timing models to account for process variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If timing violations are corrected during final stages before tape-out using flat timing model, then timing accuracy is improved, but design time increases due to multiple iterations
Solution Approach 1:
The patent applies preliminary action by performing timing violation detection and correction at block-level during early design stages rather than waiting for final tape-out stages. The system constructs block-level timing models, detects potential violations early, and inserts delay elements proactively, which reduces the need for iterative corrections later and accelerates the overall design process while maintaining timing accuracy
2Reliability
If delay elements are added to correct hold violations, then timing reliability is improved, but circuit complexity increases
Solution Approach 1:
The patent applies local quality by inserting delay elements selectively only at specific locations where timing violations are detected, rather than adding delay elements throughout the entire circuit. The block-level timing model identifies precise locations needing correction, and delay elements are added only to those specific paths, thereby improving timing reliability while minimizing the increase in overall circuit complexity
3Productivity
If block-level timing models are constructed early in design, then design process efficiency is improved, but model accuracy may be reduced compared to flat timing model
Solution Approach 1:
The patent applies segmentation by dividing the circuit into multiple blocks and constructing timing models at the block-level rather than using a single comprehensive flat timing model. This segmentation enables parallel processing and early detection of timing violations in different blocks independently, improving design process efficiency. The block-level models capture essential timing characteristics sufficient for early-stage violation detection, balancing model accuracy with processing efficiency
Data Source
AI summary
Aspects of the disclosure provide a hold violation correction method that can save design time. The method can be integrated into early stages of electric circuit design instead of correcting hold violations during the final stages of circuit design prior to tape-out. The method can include constructing block-level input/output (IO) timing models for a plurality of circuit blocks that are interconnected, detecting one or more paths between the circuit blocks, adding one or more delay elements on the paths to cause that delays on the paths are within a predetermined delay target range.