Computer Aided Design TRIZ Cases
- Signal Path Verification Device for Test Configurations
Graphical signal path verification device propagates test signals to validate hardware interface configurations.
- Signal Via Placement for Multi-Layer PCB Drilling Constraints
A via placement tool adjusts signal via positions to maintain required pitch spacing in multi-layer circuit boards.
- Integrated Circuit Global Routing via Localized Region Optimization
Segmenting an integrated circuit into regions with specific constraints resolves timing, power, and yield challenges that uniform routing fails to address.
- Automated Reconfiguration of Abutted Device Chains in Circuit Design
A system automatically reconfigures abutted device chains to insert new components while maintaining structural compliance.
- Automated Circuit Design Flaw Detection via Timing Analysis
A computer-implemented method loads static timing results to automatically identify circuit design problem areas and their root causes.
- Flip-Flop Count Determination in Physical Design
Iterative flip-flop insertion reduces RTL-to-layout convergence time by matching physical counts to estimates.
- Fin Grid Alignment for Simultaneous FinFET Formation
Aligning semiconductor fins to a common grid enables simultaneous formation, reducing manufacturing complexity and cost.
- Concolic Equivalence Checking for Circuit Designs
A computing system identifies control signals and generates valid input stimuli to simulate circuit designs.
- Block-Level IO Timing Model for Circuit Hold Violation Correction
A block-level IO timing model detects paths between circuit blocks and adds delay elements to correct hold violations during early design stages.
- Race Logic Synthesis for Deterministic IC Verification
Race logic synthesis reorders and duplicates logic blocks to eliminate concurrent execution conflicts in integrated circuit designs.
- Lattice Graph Routability Model for Standard Cell Synthesis
A lattice graph routability model determines local and global metrics to guide transistor placement, resolving accuracy limits at advanced nodes.
- RC Extraction Using Location-Based Thickness Adjustments
Location-based prediction data corrects manufacturing variations for precise RC extraction.
- Adapter System for Closed-Loop ASIC and Sensor Testing
Speed adjustment adapter enables dynamic closed-loop testing of emulated ASICs with real image sensors, reducing simulation time.
- Wiring Route Delay Matching via Segment Traversal Order
Matching wire segment lengths and traversal orders across wiring paths to balance signal propagation timing.
- Equipment Service Flags for MPC Variable Propagation
Equipment service flags manage variable propagation in model predictive controllers, eliminating custom coding and multiple model maintenance.
- Delay Calculation Engine for Clock Jitter Analysis
A delay calculation engine generates timing graphs with IR drop properties to analyze clock jitter effects in integrated circuits.
- Noise-Induced Switching Prediction in Circuit Design
A prediction system analyzes circuit net features to detect noise-induced switching risks before manufacturing.
- Row Template Placement for Electronic Design Automation
A row template guides circuit component placement within defined regions to establish legal orientations and alignments.
- Self-Aligned Double Patterning Routing Constraint Graph
A routing method generates constraint graphs with trim shape nodes to optimize integrated circuit layout.
- Dynamic Waveform Propagation Model for Logic Gate Noise Analysis
A waveform propagation model synthesizer dynamically creates a circuit model from timing results to apply arbitrary voltage waveforms through logic gates.
- IC Latch-Up Check via Geometry Partitioning and Graph Analysis
Segment n-well areas with scan lines to create connectivity graphs, resolving trade-offs between analysis efficiency and measurement precision.
- Automatic Timing Constraint Generation for IC Static Analysis
A software tool analyzes integrated circuit design features to automatically generate timing constraints for static timing analysis.
- Power Analysis for Irregular Clock Logic Circuits
Aligns irregular clock edges to a master reference signal, preventing false power dips or peaks caused by under-sampling in emulation cycles.
- Shelter Unit Design for Phase Stability in RF Transmitters
A shelter unit maintains intermediate frequency phase stability during transmission switching by compensating load changes without increasing power consumption.
- Retargeting Edge Fragments via Process Window Simulation
Retarget edge fragments using process window simulation to balance constraints, reducing lithography hotspots and improving pattern fidelity.
- High-Level Synthesis RTL Circuit Generation with User Scheduling Control
A high-level synthesis device creates register transfer level circuits using user-defined scheduling information.
- Dynamic Power Recovery in EDA Signoff Timing Analysis
A dynamic power recovery system concurrently performs cell downsizing and upsizing within a single timing signoff pass.
- Miller Coefficient Estimation via Reduced Order System Synthesis
Synthesizes reduced order systems to calculate Miller coefficients, resolving timing estimation errors from complex signal path interactions.
- RTL Hotspot Analysis for Physical Implementation Issues
A computing system analyzes logic cell metrics to identify critical physical implementation hotspots in pre-placement integrated circuit designs.
- Automated Internal Interface Generation for Hardware Modules
A tool automates internal data interface generation by analyzing gateway protocols and synthesizing integrated code for hardware realization.
- Dangling Metal Route Detection in Semiconductor Chip Design
Partition and analysis components detect long dangling metal routes to prevent antenna violations, noise, and circuit breakdown.
- Debugging Tool Simplifies Counterexample Traces for Formal Verification
A debugging tool applies soft constraints to counterexample traces to simplify waveform appearance.