Self-Aligned Double Patterning Routing Constraint Graph
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Solution Overview
Problem
In integrated circuit manufacturing, self-aligned double patterning (SADP) requires precise placement of trim shapes to create discontinuities in continuous wire tracks, posing challenges in avoiding design rule violations and ensuring accurate routing.
Innovation Solution
A method is developed to generate a routing result using self-aligned double patterning-aware routing, which involves creating an initial constraint graph with trim shapes as nodes and arcs representing spacing constraints, subdividing the graph into subgraphs for parallel optimization, and determining the final positions of trim shapes and extents to ensure compliance with design rules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If trim shapes are placed to create discontinuities in continuous wire tracks, then routing functionality is achieved, but design rule violations may occur
Solution Approach 1:
The router performs preliminary placement of trim shapes based on the initial routing result before final validation. This preliminary action allows the system to establish discontinuities in wire tracks while maintaining the ability to adjust and validate placements against design rules, thus achieving routing functionality while preventing design rule violations.
Solution Approach 2:
The system implements a feedback mechanism where the router validates trim shape placements against design rules and adjusts placements accordingly. The router receives feedback about potential design rule violations and modifies the routing result to ensure compliance, thereby maintaining both routing functionality and design rule adherence.
2Manufacturing precision
If multiple continuous track patterns are used for SADP, then manufacturing precision is improved, but routing complexity increases
Solution Approach 1:
The router segments the routing problem into distinct components: initial routing result generation, constraint graph creation, and trim shape placement. This segmentation allows each component to be optimized independently for SADP manufacturing precision while managing overall routing complexity through modular processing steps.
Solution Approach 2:
The constraint graph serves as an intermediary data structure that bridges the initial routing result and the final trim shape placements. This intermediary representation simplifies the complex relationships between multiple continuous track patterns, making the routing process more manageable while preserving SADP manufacturing precision requirements.
3Manufacturing precision
If trim shapes are precisely placed to define discontinuities, then manufacturing precision is improved, but processing time increases
Solution Approach 1:
The router performs preliminary placement of trim shapes based on the initial routing result before final validation and adjustment. This preliminary action establishes a starting configuration that requires minimal subsequent adjustment, thereby achieving precise trim shape placement while reducing overall processing time.
Solution Approach 2:
The system uses the initial routing result to automatically generate a preliminary trim shape placement configuration without requiring extensive manual intervention or iterative optimization. This self-service approach achieves precise placement accuracy while minimizing processing time by leveraging the existing routing information.
Data Source
AI summary
A method of generating a routing result to manufacture an integrated circuit using self-aligned double patterning includes generating an initial routing result that indicates a location and length of connections between components, and generating an initial constraint graph with trim shapes indicating gaps in the connections being represented as nodes and with arcs indicating relative position constraints between a pair of the nodes. The method also includes subdividing the initial constraint graph into two or more subgraphs, determining a final position of each of the nodes in the two or more subgraphs, and generating a routed design with the trim shapes having the final position of corresponding ones of the nodes relative to the connections and with extents filling in spaces between one or more of the trim shapes and associated connections. The routed design is provided for manufacture of the integrated circuit.