Hierarchical Context-Based Model for Efficient Electrical Rule Checking
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Solution Overview
Problem
Modern integrated circuits with billions of transistors pose a challenge for sign-off tests like Electrical Rule Check (ERC), as these tests consume vast amounts of computer resources and run for extended periods due to the complexity of flattening the design database.
Innovation Solution
The method involves creating a hierarchical context-based model of the integrated circuit, where a root cell represents the complete IC, and lower-level cells represent atomic design entities. Electrical properties are propagated through this hierarchy, allowing for efficient detection of electrical rule violations without flattening the model.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a flattened design database model is used for ERC testing, then complete electrical rule validation can be achieved, but memory requirements and processing time increase significantly
Solution Approach 1:
The patent segments the design database into a hierarchical structure with multiple levels (top-level circuit, subsystems, modules, and individual components). Each level maintains its own context and electrical properties, allowing ERC testing to be performed on segmented portions rather than requiring the entire flattened database in memory simultaneously. This segmentation enables complete validation while reducing peak memory requirements.
Solution Approach 2:
The patent implements a nested hierarchical model where lower-level design entities are contained within higher-level containers. The hierarchy preserves the complete electrical connectivity information through defined relationships between levels, allowing full ERC validation capability while storing data in a compact nested structure that requires less memory than a fully flattened representation.
2Reliability
If a flattened design database model is used for ERC testing, then complete electrical rule validation can be achieved, but processing time increases to many hours
Solution Approach 1:
The hierarchical segmentation allows ERC testing to proceed level-by-level through the design structure. The system can validate electrical rules at each hierarchy level independently and progressively, rather than requiring complete flattening and processing of the entire design database at once. This segmented approach dramatically reduces processing time while maintaining validation completeness.
Solution Approach 2:
The patent performs preliminary electrical property propagation and validation at upper hierarchy levels before descending to lower levels. By pre-computing and caching electrical characteristics at each hierarchy level, the system avoids redundant computations when validating lower-level details, significantly reducing overall processing time while ensuring complete ERC validation.
3Productivity
If a hierarchical context-based model is used, then memory requirements and processing time are reduced, but electrical rule checking complexity increases
Solution Approach 1:
The patent implements a universal hierarchical framework that handles multiple ERC validation tasks through a single unified model structure. The same hierarchy serves both as the organizational structure for storing design data and as the validation pathway for electrical rule checking. This multi-functionality reduces the need for separate complex data structures, thereby reducing overall system complexity while improving productivity.
Solution Approach 2:
The patent introduces intermediary context structures at each hierarchy level that mediate between upper and lower levels. These context intermediaries pre-process and summarize electrical properties, simplifying the information that must be passed between hierarchy levels. This intermediary layer reduces the complexity of direct multi-level interactions while maintaining complete ERC validation capability.
Data Source
AI summary
A method for checking electrical rules in a design of a circuit including transistors connected by nodes, includes defining a hierarchical database including (i) a root representing the circuit, and (ii) instances of context-cells representing design entities and including node-ports that connect the design entities. Electrical properties of the node-ports are propagated from the root through the node-ports to at least a portion of the context-cells. The electrical properties, which were propagated from the root, are propagated from one or more of the context-cells to one or more peer context-cells. An electrical rule violation in at least one of the context-cells is identified based on the propagated electrical properties.