Debugging Tool Simplifies Counterexample Traces for Formal Verification
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Solution Overview
Problem
Existing formal verification tools for circuit designs struggle to help designers understand counterexamples, as the cause of property failures is not always obvious, making it difficult to debug the circuit design effectively.
Innovation Solution
A debugging tool that applies soft constraints to counterexample traces to simplify their appearance, allowing designers to focus on relevant aspects and prioritize constraints for better understanding and debugging, while also enabling power analysis through similar trace manipulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If formal verification is performed on complex circuit designs, then verification completeness is improved, but trace complexity increases making debugging difficult
Solution Approach 1:
The patent extracts and removes irrelevant portions of counterexample traces while preserving the essential failure information. The debugging tool identifies and eliminates redundant signal cycles and irrelevant circuit portions from the trace, leaving only the critical path that demonstrates the property violation. This extraction process reduces trace complexity while maintaining verification reliability.
Solution Approach 2:
The patent segments the complex counterexample trace into meaningful portions: relevant signals that directly cause the property failure and irrelevant signals that can be safely removed. The tool divides the trace into critical path segments and non-critical segments, allowing selective display of only the essential failure information to designers.
2Loss of information
If all signals in counterexample trace are displayed, then trace completeness is improved, but ease of understanding deteriorates
Solution Approach 1:
The patent applies local quality by treating different signals in the trace differently based on their relevance to the property failure. Relevant signals are preserved and highlighted with higher visibility, while irrelevant signals are removed or suppressed. This differential treatment maintains the essential failure information while improving readability and ease of understanding for the designer.
3Ease of operation
If counterexample trace is simplified, then ease of debugging is improved, but trace accuracy may deteriorate
Solution Approach 1:
The patent implements feedback mechanisms where the debugging tool continuously verifies that simplified traces still accurately represent the property failure. The tool checks that the essential failure condition is preserved after simplification and provides feedback to ensure trace accuracy is maintained while achieving simplification for easier debugging.
Data Source
AI summary
The result of a property based formal verification analysis of a circuit design may include at least one counterexample for each property that is violated, which a user can use to debug the circuit design. To assist the user in this debugging process, a debugging tool applies one or more soft constraints to a counterexample trace that simplify the appearance of the trace when displayed as a waveform. The debugging tool thus facilitates a user's understanding of what parts of the counterexample trace are responsible for the property failure. Also described is a power analysis tool that increases the noise level of a trace for a circuit design in order to facilitate analysis of the circuit design's power characteristics.