IC Latch-Up Check via Geometry Partitioning and Graph Analysis
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Solution Overview
Problem
Current latch-up check processes for integrated circuit design are inefficient and inaccurate due to limitations in step size and inaccuracy when analyzing adjacent n-wells, leading to suboptimal design rule compliance and potential parasitic effects.
Innovation Solution
The approach involves partitioning the geometry into separate sections using scan lines and grid points to build connectivity graphs, allowing for accurate distance measurements and analysis of design rule compliance, including the identification of parasitic effects like latch-up.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a large size is used for area analysis in latch-up check, then the analysis step size increases and efficiency improves, but the accuracy of distance measurement between n-taps decreases
Solution Approach 1:
The patent divides the nwell area into multiple smaller regions using scan lines that partition the geometry into manageable sections. This segmentation allows the analysis to use smaller, more precise steps within each region while maintaining overall efficiency through systematic processing of divided areas.
Solution Approach 2:
The patent introduces scan lines as a new dimensional approach to analyzing the nwell geometry. By creating grid points along scan lines and building connectivity graphs, the method transforms the traditional 2D area-based analysis into a multi-dimensional framework that combines spatial partitioning with graph-theoretic distance measurement.
2Measurement precision
If the minimum spacing between adjacent nwells is used to limit size, then the analysis remains accurate for small features, but the overall analysis time increases
Solution Approach 1:
The patent segments the nwell analysis into separate regions defined by scan lines and grid points. This allows the method to apply appropriate step sizes to each segment independently, maintaining accuracy for small features while reducing overall analysis time by processing multiple segments in parallel or systematic sequences.
Solution Approach 2:
The patent dynamically adjusts analysis parameters based on the specific geometry being analyzed. By changing the step size and region definition parameters according to the actual nwell dimensions and spacing, the method optimizes both accuracy and time efficiency for each specific design scenario.
Data Source
AI summary
Disclosed is a system and method for performing latchup checks for an IC design. In one approach, partitioning is used to create separate sections of the geometry to analyze. The data is then checked by performing graph manipulations.