Wiring Route Delay Matching via Segment Traversal Order
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Solution Overview
Problem
Variations in wire segment characteristics across different wiring levels in integrated circuits lead to significant delay differences in signal propagation, making it challenging to ensure consistent timing tests and operation in the presence of process variations.
Innovation Solution
The method involves designing wiring paths to traverse wire segments of similar lengths and orientations within each wiring level, matching delay sensitivity signatures, and adjusting path lengths to minimize delay variations by ensuring that all paths traverse segments in the same order, thereby reducing the impact of process variations on signal delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If wire segments on different wiring levels are used to create wiring connections, then wiring flexibility and space utilization are improved, but delay variation increases due to process variation
Solution Approach 1:
The patent changes the parameters of wire segments by matching their lengths, orientations, and traversal orders across different wiring paths. This ensures that all paths have identical delay sensitivity signatures with respect to process variations in wire characteristics, thereby resolving the delay consistency issue while maintaining wiring flexibility through the use of multiple wiring levels
Solution Approach 2:
The patent segments wiring paths into discrete wire segments on different wiring levels and systematically matches their characteristics. By dividing the routing problem into segment-level matching, the patent achieves both wiring flexibility through multi-level routing and delay consistency through matched segment properties
2Reliability
If wire segment characteristics are matched across paths, then delay variation is reduced, but wiring path complexity increases
Solution Approach 1:
The patent applies parameter changes by systematically matching wire segment characteristics (length, orientation, traversal order) rather than optimizing each path independently. This structured approach to parameter matching reduces delay variation while avoiding the need for complex, irregular routing paths
3Quantity of substance
If wire width or thickness is reduced to increase wire resistance, then capacitance decreases, but delay increases
Solution Approach 1:
The patent addresses this trade-off by matching wire segment characteristics across paths rather than optimizing individual wire dimensions. By ensuring identical traversal of segments with matched properties, the patent achieves consistent delay behavior across paths regardless of the specific wire dimension choices made for capacitance optimization
Data Source
AI summary
A method and service of balancing delay in a circuit design begins with nodes that are to be connected together by a wiring design, or by being supplied with an initial wiring design that is to be altered. The wiring design will have many wiring paths, such as a first wiring path, a second wiring path, etc. Two or more of the wiring paths are designed to have matching timing, such that the time needed for a signal to travel along the first wiring path is about the same time needed for a signal to travel along the second wiring path, the third path, etc. The method/service designs one or all of the wiring paths to make the paths traverse wire segments of about the same length and orientation, within each wiring level that the first wiring path and the second wiring path traverse. Also, this process makes the first wiring path and the second wiring path traverse the wire segments in the same order, within each wiring level that the first wiring path and the second wiring path traverse.