Odd-Even Track Power Routing for Semiconductor Cell Reliability
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Solution Overview
Problem
The manufacturing of semiconductor devices becomes increasingly complex at miniaturized scales, leading to issues such as high yield loss, reduced reliability of electrical interconnections, and low testing coverage.
Innovation Solution
The proposed solution involves modifying the structure and manufacturing method of semiconductor devices by using standard cells with specific design layouts and biasing paths, which include odd-numbered and even-numbered tracks for conductive vias and power rails, to improve device robustness and reduce manufacturing costs and processing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If functional density is increased while geometric size is decreased, then device capability is improved, but manufacturing complexity increases leading to high yield loss and reduced reliability
Solution Approach 1:
The patent divides the standard cell into distinct regions with odd-numbered and even-numbered tracks for conductive vias and power rails. This segmentation allows separate routing paths for different electrical connections, reducing interference and improving manufacturing yield by isolating potential failure points in the interconnection structure.
Solution Approach 2:
The patent introduces a track numbering dimension (odd/even) to organize conductive vias and power rails spatially within the standard cell. This dimensional organization enables systematic routing separation, reducing manufacturing complexity by providing clear guidelines for via placement and power distribution without increasing geometric footprint.
2Manufacturing precision
If manufacturing precision is improved to reduce defects, then device robustness is enhanced, but processing time and cost increase
Solution Approach 1:
The patent establishes predetermined odd-numbered and even-numbered tracks for conductive vias and power rails during the design phase. This preliminary arrangement of routing paths eliminates the need for complex real-time via placement decisions during manufacturing, maintaining high precision while improving manufacturing efficiency through standardized, pre-planned routing structures.
3Area of stationary object
If standard cells are placed closer together to increase density, then chip area is reduced, but routing violations and manufacturing defects increase
Solution Approach 1:
By segmenting the standard cell into odd-numbered and even-numbered tracks, the patent creates well-defined boundaries for conductive vias and power rails. This segmentation maintains proper spacing and routing separation even when cells are densely packed, preventing routing violations and reducing manufacturing defects while maximizing chip area utilization.
Data Source
AI summary
A semiconductor device includes a first cell. The first cell includes: a substrate; a plurality of gate electrodes extending in a first direction and defining at least one odd-numbered track and at least one even-numbered track within the first cell, the at least one odd-numbered track alternatingly arranged with the at least one even-numbered track; a first power rail extending in a second direction perpendicular to the first direction; a first conductive via connected to the first power rail, the first conductive via being within a first odd-numbered track of the at least one odd-numbered track; a second power rail extending in the second direction; and a second conductive via connected to the second power rail, the second conductive via being within a first even-numbered track of the at least one even-numbered track.