Lattice Graph Routability Model for Standard Cell Synthesis
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Solution Overview
Problem
Conventional standard cell synthesis techniques face challenges in generating routable, complex standard cells at advanced technology nodes due to limitations in estimating routability accurately and efficiently, particularly with fewer than five routing tracks, and lack scalability for large and complex cells.
Innovation Solution
The use of a trained lattice graph routability model to determine routability metrics for local areas and global net connections, influencing transistor placement, and dynamic external pin allocation during routing, integrated with simulated annealing and genetic algorithms to optimize transistor placement and routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If sequential standard cell synthesis is used to generate transistor placement and then perform routing, then the approach can handle local areas in the standard cell, but it is inefficient or incapable of generating routable cell layouts with less than five routing tracks and lacks the ability to estimate routability accurately
Solution Approach 1:
The patent combines placement and routing operations into a simultaneous synthesis process, where both operations are performed together using a unified objective function that incorporates routability estimation. This merging allows the system to achieve accurate routability estimation while maintaining synthesis efficiency, as the coupled optimization avoids iterative sequential processing.
Solution Approach 2:
The patent implements feedback mechanisms where routability estimation results from the lattice graph model are fed back into the placement and routing optimization process. This feedback loop allows the synthesis algorithm to adjust placement and routing decisions based on real-time routability assessments, improving both accuracy and efficiency.
2Productivity
If simultaneous placement and routing mechanisms are used, then more efficient routing solutions can be generated, but they tend to lack scalability on large and complex standard cells
Solution Approach 1:
The patent segments the standard cell into a lattice graph structure where placement and routing are optimized in a hierarchical manner. The lattice graph divides the cell into manageable units (nodes and edges) that can be processed efficiently, enabling scalability to large and complex cells while maintaining the benefits of simultaneous optimization.
Solution Approach 2:
The patent changes the parameter representation by using a lattice graph model with specific mathematical parameters that capture both placement and routing constraints. This parameter transformation enables the simultaneous mechanism to scale to complex cells by representing the problem in a computationally tractable form.
3Reliability
If conventional synthesis techniques are used, then the process can be simpler, but they lack the ability to generate routable layouts at advanced technology nodes with stricter patterning rules and fewer routing tracks
Solution Approach 1:
The patent introduces a lattice graph routability model as an intermediary between the synthesis input and output. This intermediary model provides accurate routability estimation and guidance, enabling the generation of reliable layouts for advanced technology nodes while managing complexity through the structured lattice representation.
Data Source
AI summary
Lattice graph routability modelling mechanisms for standard cells utilizing a trained lattice graph routability model to determine routability metrics for local areas and global net connections in the standard cell. The metrics are applied to influence transistor placement in the standard cell, resulting in standard cell layouts with improved routability. Circuit layout generating processes are also described, in which a layout is formed lacking external pin assignments, and during routing of the nets for the circuit, a graph comprising virtual nodes and edges from the virtual nodes to grid locations for pins external to the circuit is generated. Routing to the external net of the circuit is performed according to the graph nodes and the graph edges.