Fin Grid Alignment for Simultaneous FinFET Formation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The complexity and cost of forming small FinFETs are increased due to the need for precise alignment and separate processing of semiconductor fins, which are often misaligned or have different orientations, making simultaneous formation challenging and costly.
Innovation Solution
Aligning all semiconductor fins parallel to a common grid line, allowing for simultaneous formation using diffraction techniques and shared process steps, thereby reducing manufacturing costs and complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate processing is used for misaligned fins with different orientations, then manufacturing precision can be maintained for each fin, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent merges multiple separate processing steps into a single unified process by aligning all fins to a common grid orientation. This allows simultaneously formed fins to be processed together in one etching step rather than requiring separate processing for differently oriented fins, thereby reducing device complexity while maintaining manufacturing precision through the grid alignment system
Solution Approach 2:
The patent creates a universal processing approach where a single etching process can handle all fins regardless of their specific positions, as long as they are aligned to the grid. This multi-functional processing method eliminates the need for separate processing sequences for different fin orientations, reducing overall process complexity
2Manufacturing precision
If separate processing is used for misaligned fins, then each fin can be processed independently, but manufacturing cost increases
Solution Approach 1:
The patent combines multiple separate processing operations into a single unified etching process by establishing a common grid alignment. All fins aligned to the grid can be formed simultaneously in one processing step, significantly reducing manufacturing cost compared to separate processing of misaligned fins while maintaining the required formation accuracy through grid-based positioning
3Adaptability or versatility
If fins are formed with different orientations, then design flexibility is improved, but simultaneous formation becomes challenging and costly
Solution Approach 1:
The patent resolves the conflict between design flexibility and process complexity by introducing a grid dimension as an intermediary framework. All fins are aligned to this grid dimension, allowing simultaneous formation through a single process. The grid acts as a universal reference that maintains design flexibility while enabling unified processing of all fins regardless of their functional requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the cost-effective and efficient formation of very narrow fins by ensuring all fins are aligned to the same grid lines, simplifying the manufacturing process and reducing costs associated with separate processing of misaligned or perpendicularly oriented fins.
Implementation Method 1
special optical technique such as diffraction and interference were used
Implementation Method 2
special optical technique such as diffraction and interference were used
Data Source
AI summary
A die includes at least one standard cell, which includes a first boundary and a second boundary opposite to the first boundary. The first boundary and the second boundary are parallel to a first direction. The at least one standard cell further includes a first plurality of FinFETs including first semiconductor fins parallel to the first direction. The die further includes at least one memory macro, which has a third boundary and a fourth boundary opposite to the third boundary. The third boundary and the fourth boundary are parallel to the first direction. The at least one memory macro includes a second plurality of FinFETs including second semiconductor fins parallel to the first direction. All semiconductor fins in the at least one standard cell and the at least one memory macro have pitches equal to integer times of a minimum pitch of the first and the second semiconductor fins.