Circuit Layout Checking for RTO Rule Compliance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
During the fabrication of integrated circuits, modifications due to Engineering Change Orders (ECO) often require remaking masks, leading to increased manufacturing costs due to violations of Re-Tape Out (RTO) rules, even for unmodified structures, due to the challenges of matching smaller transistor sizes and inaccurate lithography patterns.
Innovation Solution
A circuit layout checking system and method that determines whether layout patterns for logic gate array cells and filler cells exist within specific areas and checks if electrical connection layers are enclosed by metal layers with sufficient spacing, generating data to indicate compliance with layout design constraints, thereby avoiding unnecessary mask remaking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If optical proximity correction (OPC) is employed to adjust masks for smaller transistor sizes, then manufacturing precision is improved, but manufacturing cost increases due to remaking masks
Solution Approach 1:
The patent applies preliminary action by performing a checking operation before the mask making process to identify layouts that will violate RTO rules after ECO. By detecting potential violations in advance using the predetermined checking area and spacing distance criteria, the system prevents unnecessary mask remaking, thus reducing manufacturing costs while maintaining the manufacturing precision benefits of OPC for cases that truly need it.
2Manufacturing precision
If re-tape out (RTO) rules are applied to identify layouts requiring mask remaking, then manufacturing precision is improved, but productivity decreases due to increased checking operations
Solution Approach 1:
The patent applies local quality by focusing the checking operation only on specific areas around modified logic gate array cells where ECO changes occur. Instead of checking the entire layout, the system examines only the predetermined checking area extending from modified cells, applying the spacing distance criterion locally. This localized approach maintains manufacturing precision for critical areas while significantly improving productivity by reducing the scope of checking operations.
3Reliability
If layout checking is performed for all structures after ECO, then reliability is improved by preventing RTO violations, but device complexity increases due to additional checking operations
Solution Approach 1:
The patent applies the taking out principle by extracting and isolating the checking operation as a separate, dedicated process step that occurs before mask making. The checking function is separated from the main ECO and mask making workflows, allowing it to be performed independently using specific criteria (predetermined checking area, spacing distance). This extraction maintains reliability by ensuring RTO compliance checking is systematically performed while reducing overall device complexity by making the checking process modular and focused rather than embedded throughout the entire design flow.
Data Source
AI summary
A circuit layout checking method includes: determining whether there is only a first layout pattern and/or a second layout pattern corresponding to a filler cell or a second gate array cell exist in a region extending outward from the first layout pattern corresponding to a first gate array cell; determining whether a first pattern corresponding to an electrical connection layer in the first layout pattern is enclosed by a second pattern corresponding to a metal layer in the first layout pattern and whether each spacing between all boundaries of the first pattern and those of the second pattern is not less than a predetermined distance; and if there is only the first and/or second layout patterns in the first region and if the first pattern is enclosed by the second pattern and each spacing is not less than the predetermined distance, generating data indicating layout design of an integrated circuit.