High-Level Synthesis RTL Circuit Generation with User Scheduling Control
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Solution Overview
Problem
Current high-level synthesis methods struggle to create register transfer level (RTL) circuits that satisfy user-defined performance requirements, as they often require complex operation level descriptions and limited user intervention, leading to inefficient design and performance issues.
Innovation Solution
A high-level synthesis device and method that generates a register transfer level circuit using a control circuit designed by the user, without altering the operation level description, by incorporating a high-level synthesis unit, a circuit creating unit, and a circuit connecting unit to create and connect first and second RTL circuits based on user-defined scheduling and connecting information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If automatic scheduling is performed by high-level synthesis tool, then processing speed is improved, but user control over scheduling is lost
Solution Approach 1:
The scheduling process is segmented into two parts: automatic scheduling by the high-level synthesis tool for general optimization, and manual user intervention for specific scheduling adjustments. This allows both automatic processing speed improvement and user control to coexist by dividing the scheduling authority between automated and manual domains.
Solution Approach 2:
The scheduling mechanism is made dynamic by allowing users to intervene and modify scheduling decisions at runtime or during synthesis based on performance requirements. The system transitions from purely automatic to a hybrid mode where user preferences can override or supplement automated scheduling decisions.
2Adaptability or versatility
If operation level description is changed to express parallel processes, then scheduling flexibility is improved, but description complexity increases
Solution Approach 1:
Instead of requiring users to describe parallel processes explicitly in the operation level description (which increases complexity), the system inverts the approach by allowing sequential descriptions to be automatically transformed into parallel schedules by the synthesis tool. Users can specify desired performance outcomes rather than detailed parallel structures.
Solution Approach 2:
The high-level synthesis tool acts as an intermediary that translates between simple operation level descriptions and complex scheduling requirements. It mediates between the user's high-level intent and the detailed parallel process implementation, automatically generating the necessary scheduling without requiring users to write complex parallel descriptions.
3Area of stationary object
If resource sharing is performed to reduce circuit area, then area is reduced, but control circuit complexity increases
Solution Approach 1:
Resources are designed to be universal and multi-functional, capable of performing multiple different operations at different times. A single resource unit can execute different arithmetic operations by receiving different control signals, eliminating the need for dedicated resources for each operation type and reducing overall circuit area while managing complexity through standardized interfaces.
Data Source
AI summary
A high-level synthesis unit creates a first register transfer level circuit from an operation level description. A circuit creating unit creates a second register transfer level circuit based on circuit information for creating an additional circuit to be added to the first register transfer level circuit. A circuit connecting unit connects the first register transfer level circuit with the second register transfer level circuit, based on connecting information describing a connecting relation between a signal in the first register transfer level circuit and a signal in the second register transfer level circuit.