Convergence Verification for Hierarchical Domain Crossings
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Solution Overview
Problem
Current domain crossing analysis tools in integrated circuit (IC) design lack a mechanism to verify assumptions made by circuit designers, particularly before synthesis, and are not linked to implementation verification tools, leading to potential system errors due to unverified domain crossing issues.
Innovation Solution
A technique for convergence verification that involves receiving a data object representation of a circuit block, identifying synchronization schemes within a threshold flip-flop depth, and generating convergence information based on the type and depth of these schemes to output for further verification and synthesis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If automated design tools are used to design ICs, then productivity is improved, but reliability deteriorates due to unverified domain crossing issues
Solution Approach 1:
The patent applies preliminary action by performing convergence verification before synthesis and implementation. The system analyzes domain crossing issues and generates convergence information in advance, allowing designers to resolve potential problems before they manifest as system errors in the final IC implementation.
Solution Approach 2:
The patent implements feedback by providing convergence information back to the design process. The system analyzes domain crossing issues and feeds convergence information to both the synthesis tool and the designer, enabling iterative refinement of the design to ensure reliability while maintaining productivity.
2Reliability
If domain crossing analysis is performed manually, then reliability is improved through verification, but productivity deteriorates due to time consumption
Solution Approach 1:
The patent applies self-service by enabling the synthesis tool to automatically perform convergence verification using convergence information generated from domain crossing analysis. This eliminates the need for manual verification while maintaining reliability, as the system self-verifies assumptions about domain crossings during the synthesis process.
Solution Approach 2:
The patent merges convergence verification with the synthesis process. By integrating the verification function into the synthesis tool and using convergence information from domain crossing analysis, the system combines what were previously separate manual verification steps into an automated, unified process that maintains both reliability and productivity.
3Reliability
If convergence verification is integrated into synthesis tools, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by designing the convergence verification system to work within existing synthesis tool frameworks. The verification function is integrated into the synthesis tool's existing architecture, allowing it to handle multiple verification tasks through a unified system rather than requiring separate complex verification tools.
Solution Approach 2:
The patent uses convergence information as an intermediary between domain crossing analysis and synthesis verification. This intermediary data structure simplifies the integration by providing a standardized interface that connects the domain crossing analysis results to the synthesis verification process, reducing the overall complexity of the integrated system.
Data Source
AI summary
A technique for convergence verification including receiving a data object representation of a first circuit block, receiving one or more assumptions associated with the first circuit block, identifying a synchronization scheme coupled to a port of the first circuit block, determining that the synchronization scheme is within a threshold flip-flop depth, identifying, based on the determination that the synchronization scheme is within the threshold flip-flop depth, a type of the synchronization scheme and a flip-flop depth between the synchronization scheme and the port, generating first convergence information for the first circuit block based on the identified type and flip-flop depth of the synchronization scheme, and outputting the generated convergence information.