Flip-Flop Count Determination in Physical Design
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Solution Overview
Problem
In VLSI circuit design, the insertion of flip-flops in physical design often leads to discrepancies between Register-Transfer-Level (RTL) estimations and physical implementations, causing prolonged RTL-to-layout convergence time and requiring significant modifications to routing or logic design.
Innovation Solution
A computer-implemented method for automatically performing flip-flop insertions in physical design using RTL-estimated count limits, which involves synthesizing RTL designs into physical layouts, performing timing analyses, and iteratively adjusting timing variables to satisfy timing requirements without altering routing or logic design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If automatic flip-flop insertion is performed based on RTL specifications, then the RTL-to-layout convergence time is reduced, but the flip-flop insertion count in physical implementation does not match the RTL estimations
Solution Approach 1:
The patent implements a feedback mechanism where the physical implementation results (actual flip-flop counts and locations) are compared with RTL estimations, and this information is fed back to adjust subsequent insertion decisions. This closed-loop approach allows the system to learn from discrepancies and improve alignment between RTL estimates and physical reality over iterations.
Solution Approach 2:
The patent dynamically adjusts key parameters including flip-flop insertion count, placement locations, and timing constraints based on the comparison between RTL estimations and physical implementation results. By changing these parameters adaptively, the system resolves the contradiction between speed and accuracy in flip-flop insertion.
2Reliability
If flip-flops are inserted to meet timing constraints, then timing requirements are satisfied, but significant modifications to routing or logic design are required
Solution Approach 1:
The patent performs preliminary flip-flop insertions during the RTL estimation phase, establishing predicted insertion counts and locations before physical implementation. This advance planning allows timing constraints to be addressed early, reducing the need for later routing or logic design modifications.
Solution Approach 2:
The patent divides the flip-flop insertion process into separate, independent stages: RTL estimation, physical implementation, and verification/adjustment. By segmenting the process, timing constraints can be satisfied through controlled insertions without requiring comprehensive modifications to routing or logic design.
3Measurement precision
If manual verification of flip-flop counts is performed for each net, then implementation accuracy is verified, but the process becomes extremely time-consuming
Solution Approach 1:
The patent creates a digital model or representation of flip-flop insertions that mirrors the physical implementation. This copy can be automatically analyzed and verified without manual inspection, maintaining verification accuracy while dramatically reducing the time required. The system uses automated comparison between RTL estimates and physical results rather than manual net-by-net verification.
Data Source
AI summary
System and method of determining flip-flop counts of interconnects of a physical layout during integrated circuit (IC) design. The outputs of each logic block are defined as primary inputs, and the inputs of each logic block are defined as primary outputs. Each interconnect is traversed from a primary input a primary output to identify the flip-flops and determine the flip-flop count. If an interconnect has a greater flip-flop count than an RTL estimated count, measures are taken to reduce the need for flip-flops with the current routing design. If the interconnect has a smaller flip-flop count than an RTL estimated count, additional flip-flops are inserted.