Signal Pin Assignment with Asymmetric Delay Compensation
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Solution Overview
Problem
Existing circuit design methods fail to optimally assign signals to pins with asymmetric delays, leading to increased processing time due to late arriving signals being matched with pins having large processing delays, as they do not account for the rerouting delays effectively.
Innovation Solution
A method that determines latency for each signal-pin combination by considering arrival time, transit delay, and processing delay, and adjusts a latency threshold to find the maximum number of signals that can be matched with pins having latencies within the threshold, ensuring optimal pin assignment by using a system with processors and memory to analyze and store valid signal-to-pin assignments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If signals are assigned to pins using simple sorting by arrival time and processing delay, then the assignment process is simple and fast, but the longest delay is not minimized optimally because rerouting delays are not accounted for
Solution Approach 1:
The patent introduces an intermediary computational process that calculates rerouting delays and uses these calculations to optimize signal-to-pin assignments. This intermediary layer of computation mediates between the simple sorting approach and the optimal assignment goal, allowing the system to account for rerouting effects without requiring complete redesign of the assignment process
Solution Approach 2:
The patent performs preliminary calculations of rerouting delays for all possible signal-to-pin assignments before making the final assignment decisions. By calculating these delays in advance and storing them in a data structure, the system prepares optimization information beforehand, enabling optimal assignments to be made based on pre-computed data rather than complex real-time calculations
2Ease of operation
If late arriving signals are assigned to pins with large processing delays, then the assignment is straightforward, but the overall processing time increases
Solution Approach 1:
The patent inverts the conventional wisdom by not simply assigning early-arriving signals to pins with longest delays, but instead using a comprehensive latency calculation that includes rerouting delays. This inversion allows the system to identify assignments that minimize overall latency rather than following the intuitive but suboptimal approach of matching arrival time with processing delay
Solution Approach 2:
The patent changes the parameters used for assignment by introducing rerouting delay as a new parameter and combining it with arrival time and processing delay to create a comprehensive latency metric. This parameter change transforms the assignment criterion from simple sorting on individual parameters to optimization based on a composite parameter that captures the total delay
3Manufacturing precision
If comprehensive latency calculation including rerouting delays is performed for all signal-pin combinations, then optimal assignments are achieved, but the computational complexity increases
Solution Approach 1:
The patent segments the latency calculation into distinct components: arrival time at driver pin, rerouting delay through the routing network, and processing delay at the input pin. By segmenting the calculation, the system can compute each component separately and combine them, making the overall complex calculation more manageable and enabling efficient implementation through modular computation
Data Source
AI summary
A method is provided for assigning signals to input pins of a component subject to asymmetric delays. A latency is determined for each signal-pin combination of the plurality of signals and plurality of input pins. The latency is determined as a function of an arrival time of the signal, a time to route the signal from to the input pin, and a time attributable to processing by the component. A latency threshold is selected. Signal to pin assignments using only signal-pin combinations having latencies less than or equal to the latency threshold are analyzed to determine if a one-to-one signal-to-pin assignment exists that includes all signals. The latency threshold is increased and the analysis is repeated until a valid one-to-one signal-to-pin assignment is found.