Closed-loop 1xN VLSI Design System for IC Optimization
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Solution Overview
Problem
Current integrated circuit design methodologies employ open-loop processes, leading to disjointed activities that result in lost optimizations before the logic-freeze stage, requiring manual intervention and repetitive iterations, which is time-consuming and inefficient for achieving design goals related to operating frequencies and power consumption.
Innovation Solution
The implementation of a closed-loop 1×N methodology using 1×N building blocks, which allows for the creation of physical design representations based on behavioral representations, enabling alterations through logic design, synthesis, physical design, and timing analysis tools, and maintaining optimizations throughout the design flow via back-annotation and reassembly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If an open-loop design process is used with separate logic capture and physical realization activities, then the design process can be simplified and divided into distinct phases, but physical optimizations are lost during iterations before logic-freeze stage
Solution Approach 1:
The patent implements a closed-loop design system where physical design representations are fed back to logic design tools through back-annotation. This feedback mechanism allows physical optimizations (such as gate-level modifications, timing adjustments, and power optimizations) to be preserved and reused across design iterations, preventing the loss of valuable optimization information that occurs in traditional open-loop processes.
Solution Approach 2:
The patent segments the design representation into multiple views (behavioral RTL, logical gate-level, and physical implementation) that can be independently manipulated and transformed. This segmentation allows different teams to work on different aspects simultaneously while maintaining coherence through the unified 1×N building block framework, resolving the contradiction between process simplicity and information preservation.
2Reliability
If manual instantiation of gates and manual changes to synthesis flow are used to maintain physical optimizations, then design goals can be achieved, but considerable time and manual intervention are required
Solution Approach 1:
The patent enables the design system to automatically maintain and propagate physical optimizations through the design flow. The closed-loop architecture with automated back-annotation and reassembly allows the system to self-update logical and behavioral representations based on physical design changes, eliminating the need for manual intervention while ensuring design goals are met.
Solution Approach 2:
The patent performs preliminary transformations of physical design representations into logical and behavioral formats in advance, so that when design iterations occur, the optimizations are already prepared and can be automatically applied. This preliminary action eliminates the need for time-consuming manual adjustments during each iteration cycle.
3Ease of manufacture
If specific logic functions have one-for-one physical realizations with fixed entities, then design implementation is straightforward, but designers must know details at very early stage and cannot easily optimize
Solution Approach 1:
The patent transforms fixed one-for-one logic-physical mappings into dynamic, multi-view representations. The 1×N building block framework allows the same logical function to have multiple physical realizations that can be explored and optimized throughout the design process. Designers can switch between behavioral, logical, and physical views to make optimizations without being constrained by early fixed decisions.
Solution Approach 2:
The patent creates a universal 1×N building block representation that serves multiple functions: it can represent behavioral RTL, logical gate-level designs, and physical implementations within a single unified framework. This multi-functionality allows designers to work with abstract representations early in the process and progressively refine them into physical implementations, maintaining flexibility throughout the design flow.
Data Source
AI summary
Embodiments that design integrated circuits using a closed loop 1×N methodology are disclosed. Some embodiments create a physical design representation based on a behavioral representation of a design for an integrated circuit. The behavioral representation may comprise RTL HDL with one or more 1×N building blocks. The embodiments may alter elements of the 1×N building block by using logic design tools, synthesis tools, physical design tools, and timing analysis tools. Further embodiments comprise an apparatus having a viewer and a 1×N compiler. The viewer may generate displays of behavioral representations of 1×N building blocks, with the behavioral representations comprising RTL definitions. The 1×N compiler may create physical design representations of the 1×N building block and create behavioral representations from the physical design representations, wherein the physical design representations have elements altered by one or more tools of a tool suite.