Power Analysis for Irregular Clock Logic Circuits
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Solution Overview
Problem
Current power analysis tools are ineffective for design logic circuits with irregular clocks, leading to under-sampling or over-sampling of power values, resulting in false dips or peaks and potential failure of the design logic circuit in the field.
Innovation Solution
A system and method that selects a master clock with a higher frequency than the design logic clocks, aligns clock edges, determines clock periods by averaging high and low-level periods, and estimates power requirements accurately, filtering out clock cycles without level changes to avoid false readings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If power analysis is performed using irregular clocks in design logic circuits, then the analysis can be applied to more circuit types, but the measurement precision deteriorates due to under-sampling or over-sampling
Solution Approach 1:
The patent introduces a regular clock as an intermediary reference signal to synchronize power analysis measurements. By using the regular clock's stable periodicity as a reference, the system can accurately sample power consumption even when the design logic circuit uses irregular clocks. The regular clock acts as a mediator that bridges the measurement system and the irregular clock domain, ensuring consistent sampling intervals.
Solution Approach 2:
The patent dynamically adjusts the sampling parameters based on the relationship between the regular clock and irregular clocks. By changing the sampling time points to align with regular clock edges, the system maintains measurement precision regardless of the irregular clock characteristics. This parameter adjustment ensures that power analysis is performed at consistent intervals relative to the regular clock cycle.
2Measurement precision
If emulation evaluates design logic circuit once per clock event, then the analysis captures detailed power consumption, but the number of emulation cycles increases significantly
Solution Approach 1:
The patent extracts and separates the regular clock function from the irregular clock operations. By isolating the regular clock as a dedicated reference signal independent of the design logic circuit's irregular clocks, the system performs power analysis only at regular clock events rather than every clock event in the circuit. This extraction reduces the number of emulation cycles required while maintaining measurement precision for the powered-analyzed components.
Data Source
AI summary
A system is disclosed that includes a memory and a processor configured to perform operations stored in the memory. The processor performs the operations to select a master clock for a plurality of clocks in a design logic circuit. The processor further performs the operations to align a clock edge of a clock of the plurality of clocks with a corresponding nearest clock transition of the master clock. The aligned clock edge of the clock limits a number of emulation cycles for the design logic to a fixed number of emulation cycles required for the master clock The processor further performs the operation to determine a clock period for measuring power required for the design logic circuit and estimate, at the aligned clock edge, the power required for the design logic circuit corresponding to the determined clock period, which corresponds to a clock selected from the plurality of clocks and the master clock.