Multi-Die IC Placement Using Superimposition Model
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Solution Overview
Problem
The challenge in implementing integrated circuits (ICs) using multiple dies is to minimize the number of inter-die signals while ensuring efficient component placement, as manufacturing flaws can render individual dies inoperable, leading to reduced IC functionality and increased costs.
Innovation Solution
A routability-based placement method for multi-die ICs involves partitioning components among dies using a superimposition model that adjusts the relative positioning of dies to minimize inter-die signals, assigning components to hardware units based on a wire-length metric, and repositioning dies along axes to accurately estimate signal path distances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the size of the die is increased to implement a larger IC, then the IC functionality is improved, but the probability of manufacturing faults increases
Solution Approach 1:
The patent divides the IC into multiple separate dies, each implementing a portion of the overall circuit functionality. This segmentation allows the system to achieve large-scale functionality while maintaining smaller individual die sizes, thereby reducing manufacturing fault probability. The multiple dies are then integrated within a single package to function as a unified IC system.
2Reliability
If the IC is divided into multiple dies to reduce manufacturing fault impact, then reliability is improved, but the number of inter-die signals increases
Solution Approach 1:
The patent applies preliminary routing planning during the design phase to optimize the placement of components and the routing of inter-die signals. By pre-determining signal paths and component locations, the system minimizes the number of inter-die signals required while ensuring reliable fault-tolerant operation. This preliminary optimization reduces the complexity of inter-die communication without compromising reliability.
3Ease of manufacture
If conventional placement methods are used for multi-die ICs, then manufacturing is simplified, but routability and signal path accuracy deteriorate
Solution Approach 1:
The patent introduces a superimposition model that overlays the physical die layout with an idealized routing grid. This dimensional transformation allows conventional manufacturing processes to be used while achieving improved routability and signal path accuracy. The superimposition model enables precise calculation of wire-length metrics and signal path characteristics without complicating the actual manufacturing process.
Data Source
AI summary
A method of component placement for a multi-die integrated circuit (IC) can include partitioning a plurality of components of a netlist among a plurality of dies of the multi-die IC and selecting a superimposition model specifying a positioning of at least two of the plurality of dies at least partially superimposed with respect to one another. The method also can include assigning, by a processor, components of the netlist to hardware units within each of the plurality of dies according, at least in part, to a wire-length metric calculated using the superimposition model.