Concolic Equivalence Checking for Circuit Designs
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Solution Overview
Problem
Traditional equivalence checking methods for complex integrated circuit designs face scalability issues and generate invalid or redundant input stimuli due to their inability to effectively check functional equivalence across different levels of abstraction, especially when environmental constraints are not respected.
Innovation Solution
A computing system implementing concolic equivalence checking identifies control signals within circuit designs, determines realizable and unrealizable values, and generates valid input stimuli to simulate and verify the equivalence of circuit designs, avoiding redundant checks by leveraging constraint solvers and depth-first searches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If formal verification is used to check equivalence under all possible input scenarios, then measurement precision is improved, but productivity deteriorates due to scalability issues for complex designs
Solution Approach 1:
The patent applies partial action by using random testing to check a selected subset of input scenarios rather than all possible scenarios. This provides a practical balance between coverage and scalability for complex industrial designs, accepting that not every possible input combination is exhaustively tested while still achieving meaningful equivalence verification.
Solution Approach 2:
The patent applies preliminary action by using constraint solvers to pre-analyze the design and identify environmental constraints before generating test stimuli. This preliminary analysis enables the system to generate only valid stimuli that respect design constraints, avoiding wasted effort on invalid test cases and improving overall checking efficiency.
2Productivity
If random testing is used to check equivalence for a randomly selected set of input stimuli, then productivity is improved, but measurement precision deteriorates due to low coverage
Solution Approach 1:
The patent applies feedback by using constraint solvers to analyze the results of random testing and identify which input scenarios have been covered and which remain unexplored. This feedback mechanism allows the system to adaptively generate additional test stimuli to cover previously untested scenarios, thereby improving coverage while maintaining the efficiency of random testing.
Solution Approach 2:
The patent applies preliminary action by pre-processing the design to extract environmental constraints and valid input combinations before running random testing. This preliminary preparation ensures that the random testing operates within the bounds of valid design scenarios, improving both the efficiency and coverage of the equivalence checking process.
3Ease of operation
If equivalence checking is performed without respecting environmental constraints, then ease of operation is improved, but loss of information increases due to generation of invalid or redundant stimuli
Solution Approach 1:
The patent introduces constraint solvers as an intermediary component between the equivalence checking tool and the design under test. This intermediary analyzes the design to extract environmental constraints and uses them to filter and validate generated stimuli, ensuring that only valid test cases are applied while maintaining automated operation.
Solution Approach 2:
The patent applies preliminary action by performing constraint analysis and extracting environmental constraints before the equivalence checking process begins. This preliminary preparation enables the system to automatically generate valid stimuli without requiring manual intervention, maintaining ease of operation while eliminating invalid test cases.
Data Source
AI summary
This application discloses a computing system to select a set of one or more values for control signals internal to multiple circuit designs, generate input stimulus for the circuit designs based, at least in part, on the selected set of values for the control signals, and simulate the circuit designs with the input stimulus, which configures the simulated values of the control signals internal to the circuits designs to the selected set of values. The computing system can perform an equivalence check on the circuit designs using results of the simulation. The computing system can select another set of values for the control signals, and determine that at least the other set of values for the control signals are not realizable during simulation with any input stimulus.