Dynamic Waveform Propagation Model for Logic Gate Noise Analysis
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Solution Overview
Problem
Current glitch propagation analysis techniques in digital integrated circuits are inaccurate due to the approximation of noisy waveforms with effective ramp waveforms, leading to unjustified pessimism in timing analysis and the need for complex pre-characterization of logic gates, complicating the design flow.
Innovation Solution
A method that dynamically synthesizes a waveform propagation model based on timing analysis and applies an arbitrary voltage waveform derived from noise analysis to accurately determine the effect of noise on logic gates, avoiding the need for pre-characterization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If noisy waveforms are approximated with effective ramp waveforms for propagation noise analysis, then the analysis process is simplified, but the accuracy of timing analysis deteriorates and unjustified pessimism is introduced
Solution Approach 1:
The patent creates a copy of the logic gate's timing behavior through a synthesized waveform propagation model. Instead of using complex pre-characterized noise models, the invention synthesizes a simplified model that replicates the essential timing characteristics (delay and slew) of the logic gate, allowing arbitrary noisy waveforms to be propagated accurately without requiring complex pre-characterization data.
Solution Approach 2:
The patent transforms the approach by changing from fixed pre-characterized noise models to dynamically synthesized models. The waveform propagation model is synthesized based on actual timing analysis results (delay and slew values) obtained from the logic gate, allowing the model parameters to adapt to the specific timing characteristics of each gate instance rather than using generic approximations.
2Measurement precision
If pre-characterization of logic gates is performed for many combinations of logic gate environments, then noise analysis accuracy is improved, but the design flow complexity and library characterization burden increase significantly
Solution Approach 1:
The patent creates a copy of the logic gate's timing behavior through a synthesized waveform propagation model. Instead of using complex pre-characterized noise models, the invention synthesizes a simplified model that replicates the essential timing characteristics (delay and slew) of the logic gate, allowing arbitrary noisy waveforms to be propagated accurately without requiring complex pre-characterization data.
Solution Approach 2:
The waveform propagation model is synthesized automatically from the timing analysis results of the logic gate itself. The model uses the gate's own delay and slew values to create a customized propagation model, eliminating the need for external pre-characterization efforts. The system serves itself by generating the necessary characterization data from standard timing analysis rather than requiring separate library characterization processes.
3Productivity
If standard timing analysis is performed without considering noise, then the analysis speed is maintained, but the functional and timing failures due to noise glitches are not detected
Solution Approach 1:
The patent merges standard timing analysis with noise propagation analysis by integrating the waveform propagation model into the existing timing analysis framework. The synthesized model uses the same timing analysis results (delay and slew) to simultaneously evaluate both timing performance and noise susceptibility, allowing noise effects to be assessed without requiring separate analysis passes or slowing down the design flow.
Solution Approach 2:
The waveform propagation model acts as an intermediary that connects standard timing analysis with noise propagation evaluation. By using the timing analysis results to synthesize the model, the invention creates a bridge that allows noise effects to be propagated through the circuit using the same infrastructure as timing analysis, rather than requiring completely separate analysis tools or processes.
Data Source
AI summary
An approach for performing arbitrary waveform propagation through a logic gate using timing analysis results is described. In one embodiment, there is an arbitrary waveform propagation tool for determining an effect of noise on a digital integrated circuit having at least one logic gate. A timing analysis component is configured to perform a timing analysis on the at least one logic gate and a noise analysis component is configured to perform a noise analysis. A waveform propagation model synthesizer component is configured to dynamically synthesize a waveform propagation model as a function of the timing analysis. The waveform propagation model synthesizer component is further configured to apply an arbitrary voltage waveform comprising one of a noisy waveform or noise glitch waveform and determine an effect of the arbitrary voltage waveform on the at least one logic gate from the dynamically synthesized waveform propagation model.