Supplanting Metal Density Rules with Thickness Control
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Solution Overview
Problem
Conventional metal density rules in semiconductor fabrication are inadequate as they do not account for topographical variations and feature thickness, leading to incorrect determination of interconnects and increased risks of electro-migration and timing delays, especially in deep-submicron devices.
Innovation Solution
A method and system that replace rule-based design criteria with more accurate specifications for feature characteristics such as thickness and topological profiles, using models for CMP, electroplating, and other processes to predict and manage pattern-related thickness variations, allowing for more precise control over electronic design features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If metal density rules are used to control interconnect characteristics, then manufacturing simplicity is maintained, but manufacturing precision deteriorates because thickness variations are not accounted for
Solution Approach 1:
The patent changes the controlled parameter from metal density (area-based) to thickness (dimension-based). By directly specifying thickness ranges for different interconnect regions instead of controlling density percentages, the system achieves better manufacturing precision for thickness-critical features while maintaining manageable design rule complexity through region-based specifications.
Solution Approach 2:
The patent transitions from two-dimensional density control (area coverage) to three-dimensional thickness control (vertical dimension). By incorporating the thickness dimension into design rules, the system captures the actual physical characteristic that matters for electro-migration and timing, moving beyond the planar density approximation.
2Speed
If wire length is shortened to improve timing, then speed is improved, but manufacturing precision deteriorates due to increased electro-migration risk
Solution Approach 1:
The patent applies different thickness specifications to different regions of the interconnect structure. By making critical segments thicker where electro-migration risk is highest and allowing thinner sections elsewhere, the system enables shortened wire lengths for speed while maintaining reliability in high-risk areas through localized thickness enhancement.
Solution Approach 2:
The patent preemptively increases interconnect thickness in regions identified as high-risk for electro-migration before the actual failure occurs. By designing thicker interconnects in advance for shortened, high-current paths, the system cushions against the increased electro-migration risk that accompanies speed optimization through wire shortening.
3Speed
If larger gates are used to increase drive strength, then speed is improved, but use of energy worsens due to increased capacitance
Solution Approach 1:
The patent moves the optimization from gate size (transistor dimensions) to interconnect thickness (conductor dimensions). By controlling the vertical thickness of interconnect layers instead of increasing gate area, the system achieves speed improvement through better RC timing without the quadratic capacitance increase that larger gates would cause.
Solution Approach 2:
The patent changes the controlling parameter from gate width/area to interconnect thickness. By adjusting the thickness parameter of the metal layers rather than scaling up gate dimensions, the system achieves the same timing improvement while avoiding the increased gate capacitance and power dissipation associated with larger transistors.
4Speed
If low-k dielectric material is used to reduce capacitance, then speed is improved, but reliability deteriorates due to poor thermal conductivity
Solution Approach 1:
The patent shifts the optimization approach from horizontal capacitance reduction (low-k dielectric) to vertical thickness control (interconnect dimensions). By precisely controlling interconnect thickness rather than relying on low-k materials, the system achieves speed improvement through reduced RC delay without compromising thermal conductivity, since the standard dielectric material is retained.
Data Source
AI summary
Disclosed is an improved method, system, and computer program product for electronic designs with supplant design rules. According to some embodiments of the invention, the foundry-imposed design rules are replaced by one or more supplant design requirements which define absolute or relative threshold(s) for a design feature characteristic. Some other embodiments of the invention, the foundry-imposed design rules are replaced by one or more supplant design requirements which define one or more ranges of absolute or relative values for a design feature characteristic. Some other embodiments of the invention further provide an EDA tool which takes into account a model for the electronic design, the processing, metrological, lithographic, or imaging processing processes or techniques, and the supplant design requirements to determine whether the features of an electronic design meet the design requirements.