Voltage Drop Analysis for Multi-Phase Sequential Circuits
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Solution Overview
Problem
Current methods for voltage drop analysis in multi-phase sequential circuits are inadequate, particularly in accurately calculating voltage drops and delays due to the complexity of functional dependencies and overlapping switching currents, leading to pessimistic or optimistic results.
Innovation Solution
A voltage drop analysis tool that uses timing analysis to generate critical paths, re-evaluate new path delays, and consider functional dependencies, signal propagation, and overlapping switching currents, employing a method to pre-characterize power and ground currents using polynomial fits and triangle modeling to accurately calculate voltage drops and delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If worst case voltage drop for each gate is used to re-simulate the circuit, then voltage drop coverage is improved, but the result becomes too pessimistic
Solution Approach 1:
The patent applies local quality by considering the specific functional context of each gate along the critical path. Instead of uniformly applying worst-case voltage drop to all gates, the method selectively identifies gates whose switching activity actually contributes to the critical path delay. This is achieved by analyzing the timing windows and switching currents of individual gates, and only including those with overlapping switching periods that genuinely affect the path delay. This selective approach maintains voltage drop coverage while avoiding the pessimism of blanket worst-case application.
2Measurement precision
If functional dependencies are considered to improve accuracy, then voltage drop calculation precision is improved, but the complexity of determining overlapping switching increases
Solution Approach 1:
The patent segments the complex problem of determining overlapping switching into manageable components. It divides the critical path into individual gate segments, each with its own timing window and switching current characteristics. By analyzing each gate segment independently and then combining the results, the method manages complexity while maintaining precision. The segmentation allows systematic consideration of functional dependencies without requiring analysis of the entire circuit simultaneously.
Solution Approach 2:
The patent applies preliminary action by pre-calculating and storing timing windows and switching current characteristics for each gate before performing the critical path analysis. This preparatory work organizes the data in a structured format that facilitates efficient comparison and identification of overlapping switching periods. By having this information ready in advance, the method reduces the computational complexity during the actual voltage drop calculation while maintaining high precision.
3Measurement precision
If multi-phase sequential elements are accurately analyzed, then timing constraint evaluation is improved, but the difficulty of calculating accurate current for each gate increases
Solution Approach 1:
The patent applies dynamics by considering the time-varying nature of switching currents in multi-phase sequential circuits. Instead of using static or average current values, the method analyzes the dynamic switching behavior of gates, including the timing windows during which switching occurs. This dynamic analysis captures the transient current characteristics that are critical for accurate voltage drop calculation in multi-phase circuits, where switching events are distributed across different time intervals corresponding to different clock phases.
Data Source
AI summary
In the present invention a method to address voltage drop effect in the path based timing analysis for multi-phase sequential circuit is proposed. In calculating the new delay of the gate along the specified path the fact that stored discrete arrival times with respect to different clock phases at each node is used to determine a set of gates that can have transitions overlapping with that of the said gate. Furthermore, the said set is reduced by the logic verification step. Two step approach is adopted, the first is to evaluate the power currents for the said reduced set of gates by using pre-characterized timing library, then use these currents to calculate new VDD of the said gate along the path and obtain new delay for this gate. Some cell may have several internal transitions, the process of modeling power currents in terms of several triangles is discussed.