SoC Co-Simulation Using Programmable Logic Emulation
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Solution Overview
Problem
Existing approaches to co-simulation are inefficient due to high overhead in data exchange between hardware and software platforms during circuit design simulation, which prolongs simulation time.
Innovation Solution
A method and system that generate configuration data and testbench executable code to implement circuitry on programmable logic of a system-on-chip (SoC), allowing the processor to execute the testbench code and programmable logic to emulate the design-under-test, reducing data exchange overhead by operating within the SoC circuitry rather than through input/output channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If co-simulation is performed using separate hardware and software platforms, then emulation capability is achieved, but data exchange overhead increases and simulation time prolongs
Solution Approach 1:
The patent merges the hardware platform (programmable logic for DUT emulation) and software platform (processor for testbench execution) into a single integrated system-on-chip device. This consolidation eliminates the need for external data exchange between separate platforms, thereby reducing overhead and simulation time while maintaining full emulation capability.
Solution Approach 2:
The patent introduces an intermediary interface layer within the SoC that enables direct communication between the processor and programmable logic through standardized protocols (such as AXI or AMBA). This intermediary mechanism facilitates efficient data exchange without requiring external connectivity, thus reducing simulation time while preserving emulation functionality.
2Reliability
If co-simulation is performed using separate hardware and software platforms, then emulation capability is achieved, but data exchange overhead increases
Solution Approach 1:
The patent merges the hardware platform (programmable logic for DUT emulation) and software platform (processor for testbench execution) into a single integrated system-on-chip device. This consolidation eliminates the need for external data exchange between separate platforms, thereby reducing overhead and simulation time while maintaining full emulation capability.
3Adaptability or versatility
If design is simulated entirely on software platform, then flexibility is maintained, but simulation time increases
Solution Approach 1:
The patent segments the simulation functionality into two parts: the testbench and control logic run on the processor (software domain), while the design-under-test emulates on the programmable logic (hardware domain). This segmentation allows the system to leverage both the flexibility of software processing and the speed of hardware emulation, reducing overall simulation time while maintaining adaptability.
Solution Approach 2:
The patent enables dynamic allocation of simulation tasks between the processor and programmable logic based on the specific requirements of the design. The system can adaptively determine which portions of the design benefit most from hardware acceleration, thereby optimizing simulation time while preserving the flexibility to handle different design scenarios.
Data Source
AI summary
A system-on-chip (SoC) has programmable logic and a processor. A design tool generates configuration data to implement circuitry for emulation of a design-under-test (DUT) on the programmable logic and generates testbench executable code. The testbench executable code is configured to generate stimuli to the circuitry on the programmable logic. The processor can be configured to execute the testbench executable code and the programmable logic can be configured to implement the circuitry for emulation of the DUT.