Race Logic Synthesis for Deterministic IC Verification
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Solution Overview
Problem
The increasing complexity of large-scale integrated circuit (IC) designs leads to significant challenges in functional verification, with race logic issues causing inconsistent analysis results across different CPU environments and potentially leading to intermittent failures in IC chips. Existing methods are inadequate for detecting and eliminating race logic, especially when it is present in third-party IP blocks.
Innovation Solution
A set of race logic synthesis technologies that re-synthesize and eliminate race logic in compiled IC design databases, allowing for consistent verification across single- or multi-CPU environments by reordering or duplicating logic blocks to ensure deterministic execution, thereby eliminating concurrent assignment, reference, and invocation race conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multithreaded/multi-CPU EDA tools are used to accelerate verification, then productivity is improved, but race logic causes inconsistent analysis results and reliability deteriorates
Solution Approach 1:
The patent applies preliminary action by detecting and eliminating race logic conditions during the compilation phase, before verification execution. The system analyzes the design database, identifies concurrent execution conflicts, and transforms the logic to establish deterministic evaluation order in advance, preventing inconsistency during multi-CPU verification
Solution Approach 2:
The patent introduces an intermediary race logic detection and elimination process between the design compilation and verification execution. This intermediary analysis layer examines the design database, identifies race conditions, and transforms them into equivalent race-free logic, serving as a mediator that ensures consistent results across multi-CPU environments
2Adaptability or versatility
If race logic is present in third-party IP blocks, then adaptability is improved (reusing existing blocks), but the ability to detect and eliminate race logic worsens
Solution Approach 1:
The patent extracts and isolates race logic conditions from third-party IP blocks by analyzing the compiled design database. The system identifies race conditions regardless of their origin, separates them from the functional logic, and transforms them into equivalent race-free implementations, enabling detection and elimination in reused IP blocks
Solution Approach 2:
The patent enables the EDA tool to perform self-service by automatically detecting and eliminating race logic in the design database without requiring manual intervention or modification of third-party IP blocks. The tool analyzes, identifies, and transforms race conditions autonomously, maintaining IP block reusability while ensuring correctness
3Reliability
If logic blocks are reordered or duplicated to eliminate race conditions, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies copying by creating duplicate logic blocks with explicit evaluation order specifications. When race conditions are detected, the system generates equivalent logic copies that are evaluated in a determined sequence, ensuring reliability while managing complexity through systematic duplication rather than complex reordering
Data Source
AI summary
Techniques for performing race logic synthesis on an integrated circuit (IC) are described herein. According to one aspect of the invention, ESL (electronic system level) and any HDL (hardware description language) design source files of an IC design are compiled into a design database. Race logic analysis is performed on the IC design to detect race logic, including race logic for IPC (inter-process communication) and IPS (inter-process synchronization) objects in the IC design, by a third-party tool and/or by the same host EDA (electronic design automation) tool that will be performing race logic synthesis on the IC design, if the latter has built-in race logic audit functions. Based on the race logic audit results, race logic synthesis is performed on the design database, and getting rid of all identified race logic in the IC design, including IPC- and IPS-related race logic. This renders the EDA tool can perform concurrent analysis of the IC design, via the race-free IC design database, using multi-CPU/core computers and the results will be the same as if the EDA tool had performed serial analysis of the IC design using a single-CPU/core computer. Another aspect of the invention is outputting the re-synthesized logic in the design database to new ESL/HDL source files. User may use these revised source files to analyze the IC design using any other third-party EDA tools.