Hierarchical Block-Level Timing Constraints for IC Design Closure
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Solution Overview
Problem
The complexity of modern integrated circuits makes it challenging for electronic design automation (EDA) systems to achieve design closure within a reasonable time frame, as they struggle with synthesizing, analyzing, and optimizing numerous circuit parameters.
Innovation Solution
A system and method that generate hierarchical block-level timing constraints from chip-level constraints, allowing for independent timing analyses on block-level circuits, which can be performed in parallel across networked computer systems, facilitating faster timing closure for the entire chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If chip-level timing analysis is performed on the entire integrated circuit, then comprehensive timing constraints are obtained, but the analysis time becomes excessively long due to the large number of components
Solution Approach 1:
The patent divides the integrated circuit into multiple hierarchical blocks, where timing analysis is performed at both the chip-level and block-level. This segmentation allows the large-scale timing problem to be broken down into smaller, more manageable sub-problems that can be solved more efficiently while maintaining comprehensive timing constraint coverage.
Solution Approach 2:
The patent introduces a hierarchical dimension to the timing analysis process by creating block-level timing constraints that supplement the traditional chip-level constraints. This adds a new layer of abstraction that enables parallel processing and reduces the computational burden on single-level analysis.
2Productivity
If the integrated circuit is divided into hierarchical blocks for parallel processing, then analysis time is reduced, but the complexity of generating and coordinating block-level constraints increases
Solution Approach 1:
The patent performs preliminary identification of timing constraint points at block-level ports before generating the actual constraints. This preliminary action includes determining which ports require timing constraints and calculating their parameters in advance, which simplifies the subsequent constraint generation process and reduces coordination complexity.
Solution Approach 2:
The patent introduces block-level timing constraints as intermediary elements that bridge the gap between chip-level constraints and individual block implementations. These intermediary constraints serve as a coordination mechanism that enables parallel processing while maintaining overall timing integrity across the entire circuit.
3Manufacturing precision
If comprehensive chip-level timing constraints are enforced, then timing accuracy is maintained, but the flexibility for independent block-level optimization is reduced
Solution Approach 1:
The patent applies different levels of timing constraint detail to different parts of the circuit. Block-level timing constraints provide localized, detailed timing specifications for individual blocks, while chip-level constraints provide overall system-level timing guidance. This local quality approach allows each block to be optimized independently while maintaining global timing compliance.
Data Source
AI summary
A system and method of designing an integrated circuit capable of deriving timing constraints for individual block-level circuits of an integrated circuit that are derived from the chip-level timing constraints and analysis. The block-level timing constraints are in the form of one or more logical timing constraint points at the input and output ports of block-level circuits. Each logical timing constraint points specifies a clock source used to clock data through the port, a delay parameter specifying data propagation delay backward from an input port and forward from an output port, and any timing exception associated with the data path. Using the logical timing constraint point, the circuit design system performs independent timing analysis and optimization of each block-level circuit. The system then reassembles the block-level circuits into a modified chip-level circuit for which timing closure can be achieved.