Detecting Faulty Computer Hardware TRIZ Cases
- Incremental EDA Coverage Log Merging for Storage Reduction
Merges hardware verification coverage logs during simulation, reducing storage requirements and identifying coverage holes early.
- Voltage-Based Transient EM-IR Drop Analysis for IC Power Networks
Segmenting the power network into partitions reduces computational costs while maintaining accuracy in transient EM-IR drop analysis of integrated circuits.
- SPICE Model Calibration for Transistor Stress Simulation
Calibrating SPICE models with a substitute stress analyzer resolves the contradiction between simulation accuracy and computational time.
- Tagged Flip-Flop Debugging for Integrated Circuit Error Identification
Path name tagging links flip-flops to hardware description language specifications for automated simulation event comparison.
- Instruction Check Apparatus for Microcomputer I/O Simulation
An instruction check apparatus verifies hardware resource access during microcomputer operation simulation.
- Debug Workspace Reuse for Electronic Design Verification
Automated debug workspaces reuse relative cycle data across design revisions, reducing time spent on repetitive root cause analysis.
- Network Upgrade Recommender Using Usage Pattern Analysis
A network upgrade recommender system integrates hardware and software configuration data to generate targeted device upgrade suggestions.
- IP Generator for Early TAP Estimation in SOC Design
An IP generator creates abstract executable representations to estimate timing, area, and power characteristics of electronic system designs.
- CRC Calculation Decomposition for 3D Memory Layout Efficiency
Decomposing cyclic redundancy calculation across multiple data queue circuits eliminates through-silicon vias to reduce chip area and power consumption.
- Touch Screen Ripple Detection Using Grid Plate Imaging
A detection plate images grid lines onto a touch screen surface to reveal ripple defects through visual distortion analysis.